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Searched refs:RegAliases (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceRegAlloc.cpp340 RegAliases.resize(NumRegs); in init()
342 RegAliases[Reg] = &Target->getAliasesForRegister(RegNumT::fromInt(Reg)); in init()
423 const auto &Aliases = *RegAliases[Var->getRegNumTmp()]; in addSpillFill()
468 const auto &Aliases = *RegAliases[Item->getRegNumTmp()]; in handleActiveRangeExpiredOrInactive()
492 const auto &Aliases = *RegAliases[Item->getRegNumTmp()]; in handleInactiveRangeExpiredOrReactivated()
534 const auto &Aliases = *RegAliases[SrcVar->getRegNumTmp()]; in findRegisterPreference()
571 const auto &Aliases = *RegAliases[Item->getRegNumTmp()]; in filterFreeWithInactiveRanges()
604 *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp() in filterFreeWithPrecoloredRanges()
626 const auto &Aliases = *RegAliases[RegNum]; in allocatePrecoloredRegister()
639 const auto &Aliases = *RegAliases[Iter.PreferReg]; in allocatePreferredRegister()
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DIceRegAlloc.h131 llvm::SmallVector<const SmallBitVector *, REGS_SIZE> RegAliases; variable
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp808 BitVector RegAliases(TRI->getNumRegs()); in BreakAntiDependencies() local
927 RegAliases.reset(); in BreakAntiDependencies()
929 RegAliases.set(*AI); in BreakAntiDependencies()
935 if (!RegAliases[R]) in BreakAntiDependencies()
/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py4 class RegAliases(object): class
35 Aliases = RegAliases(Aliases)
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp790 BitVector RegAliases(TRI->getNumRegs()); in BreakAntiDependencies() local
909 RegAliases.reset(); in BreakAntiDependencies()
911 RegAliases.set(*AI); in BreakAntiDependencies()
917 if (!RegAliases[R]) in BreakAntiDependencies()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocLinearScan.cpp1047 SmallSet<unsigned, 8> RegAliases; in assignRegOrStackSlotAtInterval() local
1049 RegAliases.insert(*AS); in assignRegOrStackSlotAtInterval()
1054 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) { in assignRegOrStackSlotAtInterval()