Home
last modified time | relevance | path

Searched refs:RegAlign (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.h214 unsigned RegAlign = alignTo(Align, 4) / 4; in CC_ARM_AAPCS_Custom_Aggregate() local
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
/external/llvm/lib/Target/ARM/
DARMCallingConv.h214 unsigned RegAlign = alignTo(Align, 4) / 4; in CC_ARM_AAPCS_Custom_Aggregate() local
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp882 unsigned RegAlign = TRI->getSpillAlignment(*RC); in storeRegToStackSlot() local
915 unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai in storeRegToStackSlot()
927 unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai in storeRegToStackSlot()
948 unsigned RegAlign = TRI->getSpillAlignment(*RC); in loadRegFromStackSlot() local
975 unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai in loadRegFromStackSlot()
986 unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai in loadRegFromStackSlot()