| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 32 const RegisterClassInfo &RegClassInfo, in AllocationOrder() argument
37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| D | BreakFalseDeps.cpp | 39 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
261 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| D | RegAllocBase.cpp | 66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
134 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| D | AllocationOrder.h | 46 const RegisterClassInfo &RegClassInfo,
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| D | RegAllocBase.h | 70 RegisterClassInfo RegClassInfo; variable
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| D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in __anon572c728b0111::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| D | CriticalAntiDepBreaker.h | 42 const RegisterClassInfo &RegClassInfo; variable
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| /external/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 32 const RegisterClassInfo &RegClassInfo, in AllocationOrder() argument
37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| D | RegAllocBase.cpp | 63 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
128 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| D | AllocationOrder.h | 41 const RegisterClassInfo &RegClassInfo,
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| D | RegAllocBase.h | 66 RegisterClassInfo RegClassInfo; variable
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| D | RegAllocGreedy.cpp | 663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign()
767 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
768 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
847 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
878 unsigned MinCost = RegClassInfo.getMinCost(RC); in tryEvict()
888 OrderLimit = RegClassInfo.getLastCostChange(RC); in tryEvict()
901 << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1225 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1517 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1585 if (!RegClassInfo.isProperSubClass(CurRC)) in tryInstructionSplit()
[all …]
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| D | CriticalAntiDepBreaker.h | 37 const RegisterClassInfo &RegClassInfo; variable
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| D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in __anonccb3ce330111::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AllocationOrder.cpp | 27 const RegisterClassInfo &RegClassInfo) in AllocationOrder() argument
28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { in AllocationOrder()
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| D | RegAllocFast.cpp | 62 RegisterClassInfo RegClassInfo; member in __anonafd75e820111::RAFast
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint))) in allocVirtReg()
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC); in allocVirtReg()
765 if (RegClassInfo.isAllocatable(*I)) in AllocateBasicBlock()
896 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
985 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
1041 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
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| D | AllocationOrder.h | 41 const RegisterClassInfo &RegClassInfo);
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| D | CriticalAntiDepBreaker.h | 40 const RegisterClassInfo &RegClassInfo; variable
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| D | RegAllocBasic.cpp | 236 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
339 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
489 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg)); in selectOrSplit()
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| D | RegisterCoalescer.cpp | 91 RegisterClassInfo RegClassInfo; member in __anon626bd7810111::RegisterCoalescer
1087 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2; in shouldJoinPhys()
1106 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); in isWinToJoinCrossClass()
1136 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); in isWinToJoinCrossClass()
1141 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); in isWinToJoinCrossClass()
1828 RegClassInfo.runOnMachineFunction(fn); in runOnMachineFunction()
1861 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg))) in runOnMachineFunction()
1864 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg))) in runOnMachineFunction()
1911 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg))) in runOnMachineFunction()
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| D | CriticalAntiDepBreaker.cpp | 35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
535 if (!RegClassInfo.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
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| D | PostRASchedulerList.cpp | 84 RegisterClassInfo RegClassInfo; member in __anoneee000df0111::PostRAScheduler
212 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
239 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 224 struct RegClassInfo { struct
236 const RegClassInfo *const RCInfos; argument
246 const RegClassInfo *const RCIs,
671 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| D | MachineScheduler.h | 127 RegisterClassInfo *RegClassInfo; member
396 RegisterClassInfo *RegClassInfo;
440 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineScheduler.h | 108 RegisterClassInfo *RegClassInfo; member
356 RegisterClassInfo *RegClassInfo;
397 RegClassInfo(C->RegClassInfo), DFSResult(nullptr), in ScheduleDAGMILive()
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