Searched refs:RegHi (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
870 RegHi = RegLo; in ParseAMDGPURegister()
872 if (getParser().parseAbsoluteExpression(RegHi)) in ParseAMDGPURegister()
880 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1508 unsigned RegHi = RegLo + 1; in LowerReturn() local
1512 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); in LowerReturn()
1514 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); in LowerReturn()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 913 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
925 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
926 .addReg(RegHi) in expandPostRAPseudo()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
876 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1713 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
1727 RegHi = RegLo; in ParseAMDGPURegister()
1729 if (getParser().parseAbsoluteExpression(RegHi)) in ParseAMDGPURegister()
1737 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1032 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
1034 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3885 Variable *RegHi, *RegLo; in lowerCast() local
3890 RegHi = legalizeToReg(Ctx->getConstantInt32(Upper32Bits)); in lowerCast()
3891 _mov(Dest, RegHi, RegLo); in lowerCast()
3895 auto *RegHi = legalizeToReg(hiOperand(Var64On32)); in lowerCast() local
3896 _mov(Dest, RegHi, RegLo); in lowerCast()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1274 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
1287 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
1288 .addReg(RegHi); in expandPostRAPseudo()
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