| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 95 unsigned &RegKind);
768 unsigned RegNo, RegKind; in parseOperand() local
769 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
774 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
827 unsigned RegKind; in parseSparcAsmOperand() local
828 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
834 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
927 unsigned &RegKind) { in matchRegisterName() argument
930 RegKind = SparcOperand::rk_None; in matchRegisterName()
937 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 78 unsigned &RegKind);
781 unsigned RegNo, RegKind; in parseOperand() local
782 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
787 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
841 unsigned RegKind; in parseSparcAsmOperand() local
842 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
848 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
936 unsigned &RegKind) in matchRegisterName() argument
940 RegKind = SparcOperand::rk_None; in matchRegisterName()
947 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 99 unsigned RegKind : 4; member
165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
170 Op->Mem.RegKind = RegKind; in createMem()
199 bool isReg(RegisterKind RegKind) const { in isReg()
200 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
242 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 117 unsigned RegKind : 4; member
183 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
188 Op->Mem.RegKind = RegKind; in createMem()
221 bool isReg(RegisterKind RegKind) const { in isReg()
222 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
257 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
258 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
260 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
261 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
263 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 63 enum class RegKind { enum
81 StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
155 unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
194 RegKind MatchKind);
218 template <RegKind VectorKind>
304 RegKind Kind;
333 RegKind RegisterKind;
1012 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
1016 return Kind == k_Register && Reg.Kind == RegKind::NeonVector; in isNeonVectorReg()
1020 return Kind == k_Register && Reg.Kind == RegKind::NeonVector && in isNeonVectorRegLo()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 586 …bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1,…
587 …bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidt…
804 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind… in AddNextRegisterToList() argument
806 switch (RegKind) { in AddNextRegisterToList()
825 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, u… in ParseAMDGPURegister() argument
832 RegKind = IS_SPECIAL; in ParseAMDGPURegister()
837 RegKind = IS_VGPR; in ParseAMDGPURegister()
840 RegKind = IS_SGPR; in ParseAMDGPURegister()
843 RegKind = IS_TTMP; in ParseAMDGPURegister()
886 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 819 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister() argument
820 switch (RegKind) { in usesRegister()
884 RegisterKind RegKind, unsigned Reg1,
886 bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
889 Optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
890 void initializeGprCountSymbol(RegisterKind RegKind);
891 bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,
1632 RegisterKind RegKind, unsigned Reg1, in AddNextRegisterToList() argument
1634 switch (RegKind) { in AddNextRegisterToList()
1680 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, in ParseAMDGPURegister() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.h | 30 enum RegKind { enum
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 501 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
513 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
523 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
958 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
960 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 331 bool validateMSAIndex(int Val, int RegKind);
562 enum RegKind { enum in __anon68c73a3d0311::MipsOperand
607 RegKind Kind; /// Bitfield of the kinds it could possibly be
635 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, in CreateReg() argument
642 Op->RegIdx.Kind = RegKind; in CreateReg()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 9416 DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
9423 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 16, 8>());
9430 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 1, 64>());
9437 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 64>());
9444 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 32>());
9451 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 16>());
9458 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 32>());
9465 DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
9472 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 8>());
9479 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 16>());
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 402 bool validateMSAIndex(int Val, int RegKind);
736 enum RegKind { enum in __anonae6ab6950211::MipsOperand
797 RegKind Kind; /// Bitfield of the kinds it could possibly be
827 RegKind RegKind, in CreateReg() argument
834 Op->RegIdx.Kind = RegKind; in CreateReg()
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