Searched refs:RegLo (Results 1 – 8 of 8) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1261 unsigned RegLo = VA.getLocReg(); in LowerCall() local
1262 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
1264 if (RegLo == RISCV::X17) { in LowerCall()
1274 unsigned RegHigh = RegLo + 1; in LowerCall()
1507 unsigned RegLo = VA.getLocReg(); in LowerReturn() local
1508 unsigned RegHi = RegLo + 1; in LowerReturn()
1509 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
1511 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
861 if (getParser().parseAbsoluteExpression(RegLo)) in ParseAMDGPURegister()
870 RegHi = RegLo; in ParseAMDGPURegister()
879 RegNum = (unsigned) RegLo; in ParseAMDGPURegister()
880 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1713 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
1718 if (getParser().parseAbsoluteExpression(RegLo)) in ParseAMDGPURegister()
1727 RegHi = RegLo; in ParseAMDGPURegister()
1736 RegNum = (unsigned) RegLo; in ParseAMDGPURegister()
1737 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 912 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
922 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo()
923 .addReg(RegLo) in expandPostRAPseudo()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
875 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1031 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
1033 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3885 Variable *RegHi, *RegLo; in lowerCast() local
3889 RegLo = legalizeToReg(Ctx->getConstantInt32(Lower32Bits)); in lowerCast()
3891 _mov(Dest, RegHi, RegLo); in lowerCast()
3894 auto *RegLo = legalizeToReg(loOperand(Var64On32)); in lowerCast() local
3896 _mov(Dest, RegHi, RegLo); in lowerCast()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1273 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
1283 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo()
1284 .addReg(RegLo) in expandPostRAPseudo()
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