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Searched refs:RegMaskSlots (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DInterferenceCache.cpp162 ArrayRef<SlotIndex> RegMaskSlots; in update() local
194 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); in update()
197 for (unsigned i = 0, e = RegMaskSlots.size(); in update()
198 i != e && RegMaskSlots[i] < Limit; ++i) in update()
201 BI->First = RegMaskSlots[i]; in update()
254 for (unsigned i = RegMaskSlots.size(); in update()
255 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) in update()
259 BI->Last = RegMaskSlots[i-1].getDeadSlot(); in update()
DLiveIntervals.cpp114 RegMaskSlots.clear(); in releaseMemory()
171 for (SlotIndex Idx : RegMaskSlots) in print()
218 RMB.first = RegMaskSlots.size(); in computeRegMasks()
222 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
230 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot()); in computeRegMasks()
240 RegMaskSlots.push_back( in computeRegMasks()
246 RMB.second = RegMaskSlots.size() - RMB.first; in computeRegMasks()
1374 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(), in updateRegMaskSlots()
1376 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() && in updateRegMaskSlots()
1379 assert((RI == LIS.RegMaskSlots.begin() || in updateRegMaskSlots()
[all …]
/external/llvm/lib/CodeGen/
DInterferenceCache.cpp150 ArrayRef<SlotIndex> RegMaskSlots; in update() local
182 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); in update()
185 for (unsigned i = 0, e = RegMaskSlots.size(); in update()
186 i != e && RegMaskSlots[i] < Limit; ++i) in update()
189 BI->First = RegMaskSlots[i]; in update()
242 for (unsigned i = RegMaskSlots.size(); in update()
243 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) in update()
247 BI->Last = RegMaskSlots[i-1].getDeadSlot(); in update()
DLiveIntervalAnalysis.cpp99 RegMaskSlots.clear(); in releaseMemory()
162 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i) in print()
163 OS << ' ' << RegMaskSlots[i]; in print()
212 RMB.first = RegMaskSlots.size(); in computeRegMasks()
216 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
224 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot()); in computeRegMasks()
234 RegMaskSlots.push_back( in computeRegMasks()
240 RMB.second = RegMaskSlots.size() - RMB.first; in computeRegMasks()
1298 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(), in updateRegMaskSlots()
1300 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() && in updateRegMaskSlots()
[all …]
/external/llvm/include/llvm/CodeGen/
DLiveIntervalAnalysis.h72 SmallVector<SlotIndex, 8> RegMaskSlots; variable
239 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0)); in insertMBBInMaps()
331 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } in getRegMaskSlots()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLiveIntervals.h73 SmallVector<SlotIndex, 8> RegMaskSlots; variable
263 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0)); in insertMBBInMaps()
351 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } in getRegMaskSlots()