Searched refs:RegNum1 (Results 1 – 3 of 3) sorted by relevance
| /external/swiftshader/third_party/subzero/src/ |
| D | IceCfgNode.cpp | 379 const auto RegNum1 = Var1->getRegNum(); in sameVarOrReg() local
382 if (RegNum1 == RegNum2) in sameVarOrReg()
385 assert(Target->getAliasesForRegister(RegNum1)[RegNum2] == in sameVarOrReg()
386 Target->getAliasesForRegister(RegNum2)[RegNum1]); in sameVarOrReg()
387 return Target->getAliasesForRegister(RegNum1)[RegNum2]; in sameVarOrReg()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 891 unsigned Reg1, RegNum1, RegWidth1; in ParseAMDGPURegister() local
898 } else if (ParseAMDGPURegister(RegKind1, Reg1, RegNum1, RegWidth1)) { in ParseAMDGPURegister()
905 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) { in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1748 unsigned Reg1, RegNum1, RegWidth1; in ParseAMDGPURegister() local
1755 } else if (ParseAMDGPURegister(RegKind1, Reg1, RegNum1, RegWidth1, nullptr)) { in ParseAMDGPURegister()
1762 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) { in ParseAMDGPURegister()
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