| /external/v8/src/ |
| D | turbo-assembler.h | 120 template <typename RegType, typename... RegTypes,
123 base::is_same<Register, RegType, RegTypes...>::value ||
124 base::is_same<DoubleRegister, RegType, RegTypes...>::value>::type>
125 inline bool AreAliased(RegType first_reg, RegTypes... regs) { in AreAliased()
126 int num_different_regs = NumRegs(RegType::ListOf(first_reg, regs...)); in AreAliased()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/AsmParser/ |
| D | WebAssemblyAsmParser.cpp | 225 MVT::SimpleValueType ParseRegType(const StringRef &RegType) { in ParseRegType() argument
227 return StringSwitch<MVT::SimpleValueType>(RegType) in ParseRegType()
270 auto RegType = ParseRegType(TypePrefix); in ParseReg() local
271 GetType(StackTypes, RegNo) = RegType; in ParseReg()
276 WebAssemblyOperand::RegOp{RegNo, RegType})); in ParseReg()
279 auto RegType = GetType(StackTypes, RegNo); in ParseReg() local
284 WebAssemblyOperand::RegOp{RegNo, RegType})); in ParseReg()
495 auto RegType = ParseRegType(Lexer.getTok().getString()); in ParseDirective() local
496 if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) return true; in ParseDirective()
497 LocalTypes.push_back(RegType); in ParseDirective()
[all …]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerX86Base.h | 757 template <typename RegType, typename RmType>
758 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
812 template <typename RegType, typename T = Traits>
814 gprEncoding(const RegType Reg) { in gprEncoding()
818 template <typename RegType, typename T = Traits>
820 gprEncoding(const RegType Reg) { in gprEncoding()
824 template <typename RegType>
825 bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) { in is8BitRegisterRequiringRex()
827 std::is_same<typename std::decay<RegType>::type, ByteRegister>::value || in is8BitRegisterRequiringRex()
828 std::is_same<typename std::decay<RegType>::type, GPRRegister>::value; in is8BitRegisterRequiringRex()
[all …]
|
| D | IceTargetLoweringMIPS32.cpp | 1658 Type RegType; in addProlog() local
1660 RegType = IceType_f32; in addProlog()
1662 RegType = IceType_i32; in addProlog()
1663 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1664 StackOffset -= typeWidthInBytesOnStack(RegType); in addProlog()
1667 Func, RegType, SP, in addProlog()
1782 Type RegType; in addEpilog() local
1784 RegType = IceType_f32; in addEpilog()
1786 RegType = IceType_i32; in addEpilog()
1787 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV5.td | 907 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
915 let Inst{27-24} = RegType;
|
| D | HexagonInstrInfo.td | 1265 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1279 let Inst{27-24} = RegType;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 4794 string kind2, RegisterOperand RegType,
4797 BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
4798 [(set (AccumType RegType:$dst),
4799 (OpNode (AccumType RegType:$Rd),
4800 (InputType RegType:$Rn),
4801 (InputType RegType:$Rm)))]> {
7242 RegisterOperand RegType,
7245 BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, RegType, RegType, V128,
7247 [(set (AccumType RegType:$dst),
7248 (AccumType (OpNode (AccumType RegType:$Rd),
[all …]
|
| /external/v8/src/mips/ |
| D | assembler-mips.h | 2069 template <typename RegType>
2070 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t,
|
| D | assembler-mips.cc | 1378 template <typename RegType>
1380 RegType t, MSARegister ws, MSARegister wd) { in GenInstrMsa3R()
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 2134 template <typename RegType>
2135 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t,
|
| D | assembler-mips64.cc | 1342 template <typename RegType>
1344 RegType t, MSARegister ws, MSARegister wd) { in GenInstrMsa3R()
|
| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 4779 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
4780 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | Target.td | 110 // RegType - Specify the list ValueType of the registers in this register
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 5819 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
5820 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
|
| /external/llvm/include/llvm/Target/ |
| D | Target.td | 156 // RegType - Specify the list ValueType of the registers in this register
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | Target.td | 214 // RegType - Specify the list ValueType of the registers in this register
|