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Searched refs:RegUnitSetOrder (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.h563 std::vector<unsigned> RegUnitSetOrder; variable
722 return RegUnitSetOrder[Order]; in getRegSetIDAt()
726 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()
DCodeGenRegisters.cpp2046 RegUnitSetOrder.reserve(RegUnitSets.size()); in computeDerivedInfo()
2048 RegUnitSetOrder.push_back(Idx); in computeDerivedInfo()
2050 std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(), in computeDerivedInfo()
2056 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; in computeDerivedInfo()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h521 std::vector<unsigned> RegUnitSetOrder; variable
675 return RegUnitSetOrder[Order]; in getRegSetIDAt()
678 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()
DCodeGenRegisters.cpp1847 RegUnitSetOrder.reserve(RegUnitSets.size()); in computeDerivedInfo()
1849 RegUnitSetOrder.push_back(Idx); in computeDerivedInfo()
1851 std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(), in computeDerivedInfo()
1857 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; in computeDerivedInfo()