| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMachineFunctionInfo.cpp | 40 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in ComputeLegalValueVTs() local
42 ValueVTs.push_back(RegisterVT); in ComputeLegalValueVTs()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 138 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in ComputeLegalValueVTs() local
140 ValueVTs.push_back(RegisterVT); in ComputeLegalValueVTs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 858 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
894 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1210 MVT RegisterVT; in computeRegisterProperties() local
1213 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1214 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1274 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1287 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1321 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 227 EVT IntermediateVT, RegisterVT; in getCopyFromPartsVector() local
231 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
235 assert(RegisterVT == Parts[0].getValueType() && in getCopyFromPartsVector()
498 EVT IntermediateVT, RegisterVT; in getCopyToPartsVector() local
502 NumIntermediates, RegisterVT); in getCopyToPartsVector()
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); in RegsForValue() local
590 RegVTs.push_back(RegisterVT); in RegsForValue()
598 EVT RegisterVT = RegVTs[Value]; in areValueTypesLegal() local
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| D | FunctionLoweringInfo.cpp | 226 EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
230 unsigned R = CreateReg(RegisterVT); in CreateRegs()
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| D | TargetLowering.cpp | 656 EVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
692 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
880 EVT RegisterVT; in computeRegisterProperties() local
884 RegisterVT, this); in computeRegisterProperties()
885 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
940 EVT &RegisterVT) const { in getVectorTypeBreakdown()
947 RegisterVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
948 if (isTypeLegal(RegisterVT)) { in getVectorTypeBreakdown()
949 IntermediateVT = RegisterVT; in getVectorTypeBreakdown()
983 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1117 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1153 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1438 MVT RegisterVT; in computeRegisterProperties() local
1441 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1442 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1503 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1516 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1550 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 359 MVT RegisterVT; in getCopyFromPartsVector() local
366 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
370 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
375 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
376 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
686 MVT RegisterVT; in getCopyToPartsVector() local
692 NumIntermediates, RegisterVT); in getCopyToPartsVector()
696 NumIntermediates, RegisterVT); in getCopyToPartsVector()
702 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
763 MVT RegisterVT = in RegsForValue() local
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| D | FunctionLoweringInfo.cpp | 376 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
380 unsigned R = CreateReg(RegisterVT); in CreateRegs()
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| D | FastISel.cpp | 1144 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1148 MyFlags.VT = RegisterVT; in lowerCallTo()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 314 EVT &RegisterVT) const;
548 EVT VT1, RegisterVT; in getRegisterType() local
551 NumIntermediates, RegisterVT); in getRegisterType()
552 return RegisterVT; in getRegisterType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 421 MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(), in subTargetRegTypeForCallingConv() local
427 PushBack(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo], 0); in subTargetRegTypeForCallingConv()
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| D | MipsISelLowering.h | 303 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| D | MipsISelLowering.cpp | 137 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
139 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
140 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
141 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() in getVectorTypeBreakdownForCallingConv()
143 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); in getVectorTypeBreakdownForCallingConv()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 287 MVT RegisterVT; in getCopyFromPartsVector() local
291 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
294 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
295 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
573 MVT RegisterVT; in getCopyToPartsVector() local
577 NumIntermediates, RegisterVT); in getCopyToPartsVector()
582 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
628 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT); in RegsForValue() local
631 RegVTs.push_back(RegisterVT); in RegsForValue()
657 MVT RegisterVT = RegVTs[Value]; in getCopyFromRegs() local
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| D | FunctionLoweringInfo.cpp | 385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
389 unsigned R = CreateReg(RegisterVT); in CreateRegs()
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| D | FastISel.cpp | 927 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
931 MyFlags.VT = RegisterVT; in lowerCallTo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 715 MVT &RegisterVT) const;
722 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
724 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1133 MVT RegisterVT; in getRegisterType() local
1136 NumIntermediates, RegisterVT); in getRegisterType()
1137 return RegisterVT; in getRegisterType()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 538 MVT &RegisterVT) const;
842 MVT RegisterVT; in getRegisterType() local
845 NumIntermediates, RegisterVT); in getRegisterType()
846 return RegisterVT; in getRegisterType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 945 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
953 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
957 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
958 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
959 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()); in analyzeFormalArgumentsCompute()
963 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
971 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
975 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
977 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
978 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
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| D | SIISelLowering.h | 38 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| D | SIISelLowering.cpp | 744 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
750 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
751 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
757 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
758 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
767 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
768 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
775 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 1849 EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); in DoSelectCall() local
1853 MyFlags.VT = RegisterVT.getSimpleVT(); in DoSelectCall()
|