| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
333 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
334 if (!isAllocated(Regs[i])) in getFirstUnallocated()
336 return Regs.size(); in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
360 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
361 if (FirstUnalloc == Regs.size()) in AllocateReg()
365 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
374 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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| D | RegisterPressure.h | 258 RegSet Regs;
279 RegSet::const_iterator I = Regs.find(SparseIndex);
280 if (I == Regs.end())
289 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
302 RegSet::iterator I = Regs.find(SparseIndex);
303 if (I == Regs.end())
311 return Regs.size();
316 for (const IndexMaskPair &P : Regs) {
398 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 343 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
344 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
345 if (!isAllocated(Regs[i])) in getFirstUnallocated()
347 return Regs.size(); in getFirstUnallocated()
370 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
371 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
372 if (FirstUnalloc == Regs.size()) in AllocateReg()
376 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
384 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
385 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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| D | RegisterPressure.h | 277 RegSet Regs;
299 RegSet::const_iterator I = Regs.find(SparseIndex);
300 if (I == Regs.end())
309 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
322 RegSet::iterator I = Regs.find(SparseIndex);
323 if (I == Regs.end())
331 return Regs.size();
336 for (const IndexMaskPair &P : Regs) {
413 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 37 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass() argument
40 RegNo = Regs[RegNo]; in decodeRegisterClass()
186 const unsigned *Regs) in decodeBDAddr12Operand() argument
192 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDAddr12Operand()
199 const unsigned *Regs) in decodeBDAddr20Operand() argument
205 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDAddr20Operand()
211 const unsigned *Regs) in decodeBDXAddr12Operand() argument
218 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDXAddr12Operand()
220 MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); in decodeBDXAddr12Operand()
226 const unsigned *Regs) in decodeBDXAddr20Operand() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 84 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
86 RegNo = Regs[RegNo]; in decodeRegisterClass()
293 const unsigned *Regs) { in decodeBDAddr12Operand() argument
297 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
303 const unsigned *Regs) { in decodeBDAddr20Operand() argument
307 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
313 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
320 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
325 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 99 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping() argument
108 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMapping()
109 Record *Reg = Regs[i]->TheDef; in EmitRegMapping()
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMapping()
163 Record *Reg = Regs[i]->TheDef; in EmitRegMapping()
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runMCDesc() local
265 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in runMCDesc()
266 const CodeGenRegister *Reg = Regs[i]; in runMCDesc()
282 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in runMCDesc()
283 const CodeGenRegister &Reg = *Regs[i]; in runMCDesc()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 72 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
75 const std::deque<CodeGenRegister> &Regs,
200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
201 if (Regs.empty()) in EmitRegUnitPressure()
206 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
345 for (auto &RE : Regs) { in EmitRegMappingTables()
364 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
412 for (auto &RE : Regs) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
80 RegNo = Regs[RegNo]; in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand() argument
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand() argument
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
296 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 87 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
90 const std::deque<CodeGenRegister> &Regs,
205 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
206 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
211 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
344 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
351 for (auto &RE : Regs) { in EmitRegMappingTables()
370 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
418 for (auto &RE : Regs) { in EmitRegMappingTables()
467 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
234 if (!isAllocated(Regs[i])) in getFirstUnallocated()
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
265 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() argument
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
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| D | RegisterScavenging.h | 141 void setUsed(BitVector &Regs) { in setUsed() argument
142 RegsAvailable &= ~Regs; in setUsed()
144 void setUnused(BitVector &Regs) { in setUnused() argument
145 RegsAvailable |= Regs; in setUnused()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 561 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
589 Regs.push_back(std::make_pair(Reg, isKill)); in emitPushInst()
592 if (Regs.empty()) in emitPushInst()
594 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
598 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
599 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
600 } else if (Regs.size() == 1) { in emitPushInst()
603 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
608 Regs.clear(); in emitPushInst()
628 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | HWEventListener.h | 73 HWInstructionDispatchedEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionDispatchedEvent() argument
75 UsedPhysRegs(Regs) {} in HWInstructionDispatchedEvent()
83 HWInstructionRetiredEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
85 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.cpp | 106 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
107 while (Regs) { in EmitVFPRegSave()
109 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
110 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
120 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.cpp | 108 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
109 while (Regs) { in EmitVFPRegSave()
111 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
112 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
122 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
371 RegisterGroup Group, const unsigned *Regs,
376 const unsigned *Regs, RegisterKind RegKind);
379 MemoryKind MemKind, const unsigned *Regs,
544 const unsigned *Regs, bool IsAddress) { in parseRegister() argument
549 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
553 if (Regs) in parseRegister()
554 Reg.Num = Regs[Reg.Num]; in parseRegister()
561 const unsigned *Regs, RegisterKind Kind) { in parseRegister() argument
567 if (parseRegister(Reg, Group, Regs, IsAddress)) in parseRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 205 [&](ArrayRef<unsigned> Regs) { in lowerReturn() argument
206 MIRBuilder.buildUnmerge(Regs, VReg); in lowerReturn()
346 [&](ArrayRef<unsigned> Regs) { in lowerFormalArguments() argument
347 MIRBuilder.buildMerge(VRegs[Idx], Regs); in lowerFormalArguments()
406 [&](ArrayRef<unsigned> Regs) { in lowerCall() argument
407 MIRBuilder.buildUnmerge(Regs, OrigArg.Reg); in lowerCall()
452 [&](ArrayRef<unsigned> Regs) { in lowerCall() argument
453 NewRegs.assign(Regs.begin(), Regs.end()); in lowerCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 147 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
153 Regs->push_back(0); in allocateVRegs()
154 return *Regs; in allocateVRegs()
432 ArrayRef<unsigned> Regs = getOrCreateVRegs(LI); in translateLoad() local
436 for (unsigned i = 0; i < Regs.size(); ++i) { in translateLoad()
443 Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8, in translateLoad()
446 MIRBuilder.buildLoad(Regs[i], Addr, *MMO); in translateLoad()
559 auto &Regs = *VMap.getVRegs(U); in translateBitCast() local
562 if (!Regs.empty()) in translateBitCast()
563 MIRBuilder.buildCopy(Regs[0], SrcReg); in translateBitCast()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 399 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
403 RegisterGroup Group, const unsigned *Regs,
416 MemoryKind MemKind, const unsigned *Regs,
679 const unsigned *Regs, bool IsAddress) { in parseRegister() argument
684 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
688 if (Regs) in parseRegister()
689 Reg.Num = Regs[Reg.Num]; in parseRegister()
696 const unsigned *Regs, RegisterKind Kind) { in parseRegister() argument
702 if (parseRegister(Reg, Group, Regs, IsAddress)) in parseRegister()
834 const unsigned *Regs, RegisterKind RegKind) { in parseAddress() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 Regs.begin(), Regs.end(), rx, [&](int LHS, const int RHS) { in visitSoftInstr()
345 Regs.insert(I, rx); in visitSoftInstr()
351 while (!Regs.empty()) { in visitSoftInstr()
353 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
360 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
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| D | AggressiveAntiDepBreaker.cpp | 86 std::vector<unsigned> &Regs, in GetGroupRegs() argument
91 Regs.push_back(Reg); in GetGroupRegs()
563 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
564 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
565 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
566 if (Regs.empty()) in FindSuitableFreeRegisters()
576 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
577 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
599 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
600 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 237 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
239 for (unsigned i = 0; Regs[i]; ++i) in determineCalleeSaves()
240 if (RISCV::FPR32RegClass.contains(Regs[i]) || in determineCalleeSaves()
241 RISCV::FPR64RegClass.contains(Regs[i])) in determineCalleeSaves()
242 SavedRegs.set(Regs[i]); in determineCalleeSaves()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, in GetGroupRegs() argument
76 Regs.push_back(Reg); in GetGroupRegs()
558 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
559 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
560 assert(Regs.size() > 0 && "Empty register group!"); in FindSuitableFreeRegisters()
561 if (Regs.size() == 0) in FindSuitableFreeRegisters()
571 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
572 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
591 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
592 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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| /external/syzkaller/vendor/golang.org/x/sys/unix/ |
| D | zptracemipsle_linux.go | 12 Regs [32]uint64 member
33 Regs [32]uint64 member
|