| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMapAsm2IntrinV65.gen.td | 10 …c1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>;
11 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
12 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
13 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
14 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
15 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
16 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
18 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
19 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
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| D | HexagonDepMappings.td | 156 …= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
157 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
158 …cmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
159 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
160 …= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
161 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
162 …cmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
163 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
164 …= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
165 …mp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormatsV60.td | 46 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
52 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
58 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
64 Requires<[HasV60T, UseHVX]>;
70 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
76 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
82 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
88 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
94 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
100 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
[all …]
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| D | HexagonIntrinsicsV60.td | 67 Requires<[UseHVXSgl]>;
71 Requires<[UseHVXSgl]>;
76 Requires<[UseHVXDbl]>;
81 Requires<[UseHVXDbl]>;
87 Requires<[UseHVXSgl]>;
92 Requires<[UseHVXSgl]>;
97 Requires<[UseHVXSgl]>;
102 Requires<[UseHVXSgl]>;
107 Requires<[UseHVXSgl]>;
112 Requires<[UseHVXSgl]>;
[all …]
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| D | HexagonInstrAlias.td | 283 Requires<[UseMEMOP]>;
287 Requires<[UseMEMOP]>;
291 Requires<[UseMEMOP]>;
295 Requires<[UseMEMOP]>;
299 Requires<[UseMEMOP]>;
303 Requires<[UseMEMOP]>;
307 Requires<[UseMEMOP]>;
311 Requires<[UseMEMOP]>;
315 Requires<[UseMEMOP]>;
319 Requires<[UseMEMOP]>;
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrMPX.td | 19 Requires<[HasMPX, Not64BitMode]>;
22 Requires<[HasMPX, In64BitMode]>;
30 Requires<[HasMPX, Not64BitMode]>;
33 Requires<[HasMPX, In64BitMode]>;
36 Requires<[HasMPX, Not64BitMode]>;
39 Requires<[HasMPX, In64BitMode]>;
47 Requires<[HasMPX]>;
50 Requires<[HasMPX, Not64BitMode]>;
53 Requires<[HasMPX, In64BitMode]>;
57 Requires<[HasMPX]>;
[all …]
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| D | X86InstrVMX.td | 21 Requires<[Not64BitMode]>;
24 Requires<[In64BitMode]>;
28 Requires<[Not64BitMode]>;
31 Requires<[In64BitMode]>;
47 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
49 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
51 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
53 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
55 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
57 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
[all …]
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| D | X86InstrTSX.td | 24 Requires<[HasRTM]>;
28 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>;
30 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
34 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
42 [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
47 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
48 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;
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| D | X86InstrSystem.td | 54 Requires<[In64BitMode]>;
62 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
66 (INT3)>, Requires<[NotPS4]>;
68 (INT (i8 0x41))>, Requires<[IsPS4]>;
122 Requires<[Not64BitMode]>;
125 Requires<[In64BitMode]>;
129 Requires<[Not64BitMode]>;
132 Requires<[In64BitMode]>;
141 Requires<[Not64BitMode]>;
144 Requires<[In64BitMode]>;
[all …]
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| D | X86InstrSVM.td | 34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
58 "invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>;
61 "invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
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| D | X86InstrControl.td | 26 Requires<[Not64BitMode]>;
29 Requires<[In64BitMode]>;
36 Requires<[Not64BitMode]>;
40 Requires<[In64BitMode]>;
47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
65 IIC_IRET>, Requires<[In64BitMode]>;
122 Requires<[Not64BitMode]>;
130 Requires<[In64BitMode]>;
136 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
[all …]
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| D | X86InstrFormats.td | 525 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
528 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
532 Requires<[UseSSE1]>;
536 Requires<[UseSSE1]>;
540 Requires<[HasAVX]>;
544 Requires<[HasAVX]>;
566 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
569 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
572 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
575 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrMPX.td | 22 Requires<[HasMPX, Not64BitMode]>;
25 Requires<[HasMPX, In64BitMode]>;
33 Requires<[HasMPX, Not64BitMode]>;
36 Requires<[HasMPX, In64BitMode]>;
40 Requires<[HasMPX, Not64BitMode]>;
43 Requires<[HasMPX, In64BitMode]>;
51 Requires<[HasMPX]>, NotMemoryFoldable;
55 Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
58 Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
63 Requires<[HasMPX]>, NotMemoryFoldable;
[all …]
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| D | X86InstrSystem.td | 35 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
53 Requires<[In64BitMode]>;
59 Requires<[In64BitMode]>;
63 (INT3)>, Requires<[NotPS4]>;
65 (INT (i8 0x41))>, Requires<[IsPS4]>;
117 Requires<[Not64BitMode]>;
120 Requires<[In64BitMode]>;
124 Requires<[Not64BitMode]>;
127 Requires<[In64BitMode]>;
136 Requires<[Not64BitMode]>;
[all …]
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| D | X86InstrVMX.td | 22 Requires<[Not64BitMode]>;
25 Requires<[In64BitMode]>;
30 Requires<[Not64BitMode]>;
33 Requires<[In64BitMode]>;
53 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
56 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
61 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
64 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
69 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
72 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
[all …]
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| D | X86InstrControl.td | 25 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
27 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
31 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
33 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
39 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
45 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
55 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
111 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
118 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
124 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
[all …]
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| D | X86InstrSVM.td | 35 Requires<[Not64BitMode]>;
38 Requires<[In64BitMode]>;
43 Requires<[Not64BitMode]>;
46 Requires<[In64BitMode]>;
51 Requires<[Not64BitMode]>;
54 Requires<[In64BitMode]>;
59 "invlpga\t{%eax, %ecx|eax, ecx}", []>, TB, Requires<[Not64BitMode]>;
62 "invlpga\t{%rax, %ecx|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
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| D | X86InstrFormats.td | 567 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>;
570 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>;
574 Requires<[UseSSE1]>;
578 Requires<[UseSSE1]>;
582 Requires<[HasAVX]>;
586 Requires<[HasAVX]>;
608 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>;
611 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>;
614 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
617 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
108 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
112 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
108 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
112 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrFormats.td | 310 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
313 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
316 Requires<[HasSSE1]>;
320 Requires<[HasSSE1]>;
324 Requires<[HasAVX]>;
328 Requires<[HasAVX]>;
341 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
344 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
347 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
350 Requires<[HasSSE2]>;
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 116 Requires<[HasFullFP16]>;
135 Requires<[HasFullFP16]>;
232 Requires<[HasV8MMainline, Has8MSecExt]> {
245 Requires<[HasV8MMainline, Has8MSecExt]> {
278 Requires<[HasVFP2]>;
280 Requires<[HasVFP2]>;
282 Requires<[HasVFP2]>;
284 Requires<[HasVFP2]>;
445 Requires<[HasFullFP16]>;
451 Requires<[HasFPARMv8]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 136 Requires<[HasFullFP16]>;
155 Requires<[HasFullFP16]>;
252 Requires<[HasV8MMainline, Has8MSecExt]> {
265 Requires<[HasV8MMainline, Has8MSecExt]> {
276 Requires<[HasVFP2]>;
278 Requires<[HasVFP2]>;
280 Requires<[HasVFP2]>;
282 Requires<[HasVFP2]>;
460 Requires<[HasFullFP16]>;
466 Requires<[HasFPARMv8]>;
[all …]
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| D | ARMSystemRegister.td | 42 code Requires = [{ {} }];
47 let Requires = [{ {ARM::FeatureDSP} }] in {
73 let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
80 let Requires = [{ {ARM::HasV7Ops} }] in {
88 let Requires = [{ {ARM::Feature8MSecExt} }] in {
93 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
100 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
105 let Requires = [{ {ARM::Feature8MSecExt} }] in {
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrConv.td | 69 Requires<[HasNontrappingFPToInt]>;
74 Requires<[HasNontrappingFPToInt]>;
79 Requires<[HasNontrappingFPToInt]>;
84 Requires<[HasNontrappingFPToInt]>;
89 Requires<[HasNontrappingFPToInt]>;
94 Requires<[HasNontrappingFPToInt]>;
99 Requires<[HasNontrappingFPToInt]>;
104 Requires<[HasNontrappingFPToInt]>;
111 Requires<[NotHasNontrappingFPToInt]>;
114 Requires<[NotHasNontrappingFPToInt]>;
[all …]
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