| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 56 unsigned ReturnReg);
184 unsigned ReturnReg; variable
220 unsigned ReturnReg) override;
308 unsigned ReturnReg) override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 64 unsigned ReturnReg);
203 unsigned ReturnReg; variable
247 unsigned ReturnReg) override;
343 unsigned ReturnReg) override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 91 const MCPhysReg ReturnReg = X86::R10; in addProlog() local
96 addDirectMem(BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(ReturnReg), in addProlog()
114 .addReg(ReturnReg); in addProlog()
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| D | X86MCInstLower.cpp | 524 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; in Lower() local
527 OutMI.addOperand(MCOperand::createReg(ReturnReg)); in Lower()
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| D | X86ISelLowering.cpp | 15882 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, in GetTLSADDR() argument
15908 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); in GetTLSADDR()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8632.h | 63 Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) override;
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| D | IceTargetLoweringX8664.h | 66 Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) override;
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| D | IceTargetLoweringX8664.cpp | 619 Inst *TargetX8664::emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) { in emitCallToTarget() argument
682 if (ReturnReg != nullptr) { in emitCallToTarget()
683 Context.insert<InstFakeDef>(ReturnReg); in emitCallToTarget()
702 NewCall = Context.insert<Traits::Insts::Call>(ReturnReg, CallTarget); in emitCallToTarget()
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| D | IceTargetLoweringX8632.cpp | 344 Inst *TargetX8632::emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) { in emitCallToTarget() argument
359 return Context.insert<Traits::Insts::Call>(ReturnReg, CallTarget); in emitCallToTarget()
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| D | IceTargetLoweringMIPS32.cpp | 3482 Variable *ReturnReg = nullptr; in lowerCall() local
3495 ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_V0); in lowerCall()
3498 ReturnReg = I32Reg(RegMIPS32::Reg_V0); in lowerCall()
3502 ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_F0); in lowerCall()
3505 ReturnReg = makeReg(IceType_f64, RegMIPS32::Reg_F0); in lowerCall()
3513 ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_V0); in lowerCall()
3514 auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg); in lowerCall()
3523 ReturnReg = makeReg(IceType_i32, RegMIPS32::Reg_V0); in lowerCall()
3560 if (ReturnReg && isVectorIntegerType(ReturnReg->getType())) { in lowerCall()
3566 .jal(ReturnReg, CallTarget); in lowerCall()
[all …]
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| D | IceTargetLoweringARM32.cpp | 3780 Variable *ReturnReg = nullptr; in lowerCall() local
3795 ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_r0); in lowerCall()
3798 ReturnReg = makeReg(IceType_i32, RegARM32::Reg_r0); in lowerCall()
3802 ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_s0); in lowerCall()
3805 ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_d0); in lowerCall()
3814 ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_q0); in lowerCall()
3844 Sandboxer(this, InstBundleLock::Opt_AlignToEnd).bl(ReturnReg, CallTarget); in lowerCall()
3853 if (Instr->hasSideEffects() && ReturnReg) { in lowerCall()
3854 Context.insert<InstFakeUse>(ReturnReg); in lowerCall()
3859 if (ReturnReg != nullptr) { in lowerCall()
[all …]
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| D | IceTargetLoweringX86BaseImpl.h | 2707 Variable *ReturnReg = nullptr;
2719 ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_eax);
2723 ReturnReg = makeReg(IceType_i64, Traits::getRaxOrDie());
2725 ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
2744 ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_xmm0);
2751 Inst *NewCall = emitCallToTarget(CallTarget, ReturnReg);
2770 if (Instr->hasSideEffects() && ReturnReg) {
2771 Context.insert<InstFakeUse>(ReturnReg);
2780 assert(ReturnReg && "Vector type requires a return register");
2782 _movp(Tmp, ReturnReg);
[all …]
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| D | IceTargetLoweringMIPS32.h | 628 InstMIPS32Call *jal(Variable *ReturnReg, Operand *CallTarget);
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| D | IceTargetLoweringARM32.h | 1090 InstARM32Call *bl(Variable *ReturnReg, Operand *CallTarget);
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| D | IceTargetLoweringX86Base.h | 381 virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 66 unsigned ReturnReg) {} in emitFrame() argument
439 unsigned ReturnReg) { in emitFrame() argument
443 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n'; in emitFrame()
893 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg in emitDirectiveEnd()
977 ReturnReg = RegInfo->getEncodingValue(ReturnReg_); in emitFrame()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 75 unsigned ReturnReg) {} in emitFrame() argument
511 unsigned ReturnReg) { in emitFrame() argument
515 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n'; in emitFrame()
1007 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg in emitDirectiveEnd()
1091 ReturnReg = RegInfo->getEncodingValue(ReturnReg_); in emitFrame()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 150 unsigned ReturnReg, unsigned char OperandFlags) const;
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| D | HexagonISelLowering.cpp | 1547 GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg, in GetDynamicTLSAddr() argument
1577 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); in GetDynamicTLSAddr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 192 unsigned ReturnReg, unsigned char OperandFlags) const;
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| D | HexagonISelLowering.cpp | 1067 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg, in GetDynamicTLSAddr() argument
1096 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue); in GetDynamicTLSAddr()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1560 unsigned ReturnReg = STI.is64Bit() ? X86::RAX : X86::EAX; in emitEpilogue() local
1563 BuildMI(MBB, FirstCSPop, DL, TII.get(X86::LEA64r), ReturnReg) in emitEpilogue()
1571 BuildMI(MBB, FirstCSPop, DL, TII.get(X86::MOV32ri), ReturnReg) in emitEpilogue()
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| D | X86MCInstLower.cpp | 495 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; in Lower() local
498 OutMI.addOperand(MCOperand::createReg(ReturnReg)); in Lower()
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| D | X86ISelLowering.cpp | 12984 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, in GetTLSADDR() argument
13010 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); in GetTLSADDR()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 7368 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, in GetTLSADDR() argument
7389 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); in GetTLSADDR()
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