Searched refs:Rsrc23 (Results 1 – 4 of 4) sorted by relevance
228 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue() local237 BuildMI(MBB, I, DL, SMovB64, Rsrc23) in emitPrologue()246 uint64_t Rsrc23 = TII->getScratchRsrcWords23(); in emitPrologue() local256 .addImm(Rsrc23 & 0xffffffff) in emitPrologue()260 .addImm(Rsrc23 >> 32) in emitPrologue()
3064 uint64_t Rsrc23 = getDefaultRsrcDataFormat() | in getScratchRsrcWords23() local3070 Rsrc23 |= (EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT) | in getScratchRsrcWords23()3077 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT; in getScratchRsrcWords23()3079 return Rsrc23; in getScratchRsrcWords23()
443 uint64_t Rsrc23 = TII->getScratchRsrcWords23(); in emitEntryFunctionScratchSetup() local488 .addImm(Rsrc23 & 0xffffffff) in emitEntryFunctionScratchSetup()492 .addImm(Rsrc23 >> 32) in emitEntryFunctionScratchSetup()
4679 uint64_t Rsrc23 = getDefaultRsrcDataFormat() | in getScratchRsrcWords23() local4686 Rsrc23 |= EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT; in getScratchRsrcWords23()4690 Rsrc23 |= UINT64_C(3) << AMDGPU::RSRC_INDEX_STRIDE_SHIFT; in getScratchRsrcWords23()4695 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT; in getScratchRsrcWords23()4697 return Rsrc23; in getScratchRsrcWords23()