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Searched refs:Rt1 (Results 1 – 2 of 2) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3950 unsigned Rt1 = Inst.getOperand(1).getReg(); in validateInstruction() local
3953 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || in validateInstruction()
/external/clang/lib/CodeGen/
DCGBuiltin.cpp4071 Value *Rt1 = Builder.CreateExtractValue(RtAndRt2, 0); in EmitARMBuiltinExpr() local
4073 Rt1 = Builder.CreateZExt(Rt1, Int64Ty); in EmitARMBuiltinExpr()
4077 RtAndRt2 = Builder.CreateOr(RtAndRt2, Rt1); in EmitARMBuiltinExpr()