Searched refs:RtReg (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3031 unsigned RtReg = RtRegOp.getReg(); in expandDiv() local
3046 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) in expandDiv()
3049 if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) { in expandDiv()
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3059 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDiv()
3064 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { in expandDiv()
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3084 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3089 TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI); in expandDiv()
3092 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDiv()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3950 unsigned RtReg; in expandDivRem() local
3957 RtReg = RtOp.getReg(); in expandDivRem()
4025 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { in expandDivRem()
4037 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4047 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4052 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4055 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4083 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6225 const unsigned RtReg = Inst.getOperand(0).getReg(); in validateInstruction() local
6228 if (RtReg == ARM::LR) in validateInstruction()
6232 const unsigned Rt = MRI->getEncodingValue(RtReg); in validateInstruction()
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