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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DConcatenatedSubregs.td45 def S13 : MyReg<"s13">;
57 def D6 : MyReg<"d6", [S12, S13]>;
84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
112 // CHECK-NEXT: SubReg ssub4 = S13
124 // CHECK-NEXT: SubReg ssub3 = S13
/external/clang/test/CodeGenCXX/
Dwarn-padded-packed.cpp70 struct S13 { // expected-warning {{padding size of 'S13' with 6 bits to alignment boundary}} struct
76 void f(S1*, S2*, S3*, S4*, S5*, S6*, S7*, S8*, S9*, S10*, S11*, S12*, S13*) { } in f() argument
Dmicrosoft-abi-static-initializers.cpp72 static S S13; in MultipleStatics() local
/external/dng_sdk/source/
Ddng_fingerprint.cpp464 S13 = 17, in MD5Transform() enumerator
514 FF (c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */ in MD5Transform()
518 FF (c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */ in MD5Transform()
522 FF (c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ in MD5Transform()
526 FF (c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ in MD5Transform()
/external/ppp/pppd/
Dmd5.c212 #define S13 17 macro
216 FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
220 FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
224 FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
228 FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
/external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/crypto/digests/
DMD5Digest.java158 private static final int S13 = 17; field in MD5Digest
242 c = rotateLeft(c + F(d, a, b) + X[ 2] + 0x242070db, S13) + d; in processBlock()
246 c = rotateLeft(c + F(d, a, b) + X[ 6] + 0xa8304613, S13) + d; in processBlock()
250 c = rotateLeft(c + F(d, a, b) + X[10] + 0xffff5bb1, S13) + d; in processBlock()
254 c = rotateLeft(c + F(d, a, b) + X[14] + 0xa679438e, S13) + d; in processBlock()
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/digests/
DMD5Digest.java156 private static final int S13 = 17; field in MD5Digest
240 c = rotateLeft(c + F(d, a, b) + X[ 2] + 0x242070db, S13) + d; in processBlock()
244 c = rotateLeft(c + F(d, a, b) + X[ 6] + 0xa8304613, S13) + d; in processBlock()
248 c = rotateLeft(c + F(d, a, b) + X[10] + 0xffff5bb1, S13) + d; in processBlock()
252 c = rotateLeft(c + F(d, a, b) + X[14] + 0xa679438e, S13) + d; in processBlock()
/external/clang/test/PCH/
Dcxx-key-functions.cpp21 struct S13 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.td69 S9, S10, S11, S12, S13, S14, S15]>>,
81 S9, S10, S11, S12, S13, S14, S15]>>,
169 S9, S10, S11, S12, S13, S14, S15]>>,
181 S9, S10, S11, S12, S13, S14, S15]>>,
DARMRegisterInfo.td80 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
99 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
DARMBaseRegisterInfo.cpp711 case ARM::S13: return ARM::S12; in getRegisterPairEven()
764 case ARM::S12: return ARM::S13; in getRegisterPairOdd()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td78 S9, S10, S11, S12, S13, S14, S15]>>,
97 S9, S10, S11, S12, S13, S14, S15]>>,
219 S9, S10, S11, S12, S13, S14, S15]>>,
237 S9, S10, S11, S12, S13, S14, S15]>>,
DARMCallingConv.h168 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
DARMRegisterInfo.td99 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
118 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
/external/llvm/lib/Target/ARM/
DARMCallingConv.td78 S9, S10, S11, S12, S13, S14, S15]>>,
97 S9, S10, S11, S12, S13, S14, S15]>>,
218 S9, S10, S11, S12, S13, S14, S15]>>,
236 S9, S10, S11, S12, S13, S14, S15]>>,
DARMCallingConv.h168 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
DARMRegisterInfo.td87 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
106 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h168 case SP: case S13: case D13: case Q13: return 13; in getARMRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc295 …:S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
531 …:S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
740 …:S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
889 …:S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp54 case AArch64::S13: in isOdd()
DAArch64RegisterInfo.td317 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
352 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp54 case AArch64::S13: in isOdd()
DAArch64RegisterInfo.td298 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
333 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
/external/eigen/Eigen/src/Core/arch/AVX512/
DPacketMath.h1079 __m512 S13 = _mm512_shuffle_ps(T12, T14, _MM_SHUFFLE(3, 2, 3, 2));
1096 EIGEN_EXTRACT_8f_FROM_16f(S13, S13);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp233 PPC::S12, PPC::S13, PPC::S14, PPC::S15,

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