| /external/llvm/test/CodeGen/X86/ |
| D | win64_frame.ll | 2 ; RUN: llc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s --check-prefix=SAHF
160 ; SAHF: lock cmpxchgq
161 ; SAHF-NEXT: seto %al
162 ; SAHF-NEXT: lahf
171 ; SAHF: callq dummy
172 ; SAHF-NEXT: pushq
173 ; SAHF: addb $127, %al
174 ; SAHF-NEXT: sahf
175 ; SAHF-NEXT: popq
|
| D | eflags-copy-expansion.mir | 57 ; CHECK-NEXT: SAHF implicit-def %eflags, implicit %ah
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | cmpxchg-clobber-flags.ll | 7 …u -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
8 …strs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF
9 …u -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
|
| D | win64_frame.ll | 3 …lc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s --check-prefix=ALL --check-prefix=SAHF
|
| D | flags-copy-lowering.mir | 3 # Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 523 SAHF, enumerator
|
| D | X86.td | 200 "Support LAHF and SAHF instructions">;
|
| D | X86SchedHaswell.td | 502 // LAHF SAHF.
|
| D | X86InstrInfo.td | 145 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
1584 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
|
| /external/v8/src/ |
| D | globals.h | 799 SAHF, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 546 SAHF, enumerator
|
| D | X86.td | 226 "Support LAHF and SAHF instructions">;
|
| D | X86InstrInfo.td | 151 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
1741 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
|
| /external/v8/src/x64/ |
| D | assembler-x64.cc | 89 if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF; in ProbeImpl()
117 CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(SAHF), in PrintFeatures()
2838 DCHECK(IsEnabled(SAHF)); in sahf()
|
| /external/v8/src/compiler/x64/ |
| D | code-generator-x64.cc | 1317 if (CpuFeatures::IsSupported(SAHF)) { in AssembleArchInstruction()
1318 CpuFeatureScope sahf_scope(tasm(), SAHF); in AssembleArchInstruction()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 600 #define SAHF CHOICE(sahf, sahf, sahf) macro
1313 #define SAHF sahf macro
|
| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1_reduce.inc | 1224 2914U, // SAHF
|
| D | X86GenAsmWriter_reduce.inc | 1224 4838U, // SAHF
|
| D | X86GenAsmWriter.inc | 2474 14414U, // SAHF
8745 0U, // SAHF
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.td | 983 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
|
| D | X86GenAsmWriter.inc | 2275 8016U, // SAHF
6158 "QRTSSm\000RSQRTSSm_Int\000RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000"
|
| D | X86GenAsmWriter1.inc | 2275 5982U, // SAHF
6901 "QRTSSm\000RSQRTSSm_Int\000RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000"
|
| D | X86GenInstrInfo.inc | 2278 SAHF = 2262,
6446 …{ 2262, 0, 0, 0, 0, "SAHF", 0, 0x13c000001ULL, ImplicitList27, ImplicitList1, 0 }, // Inst #2262 …
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | CodeGenerator.rst | 403 MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
|
| /external/llvm/docs/ |
| D | CodeGenerator.rst | 403 MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
|