1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2 /* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. 5 */ 6 /* OSCILLATOR clocks */ 7 #define CK_HSE 0 8 #define CK_CSI 1 9 #define CK_LSI 2 10 #define CK_LSE 3 11 #define CK_HSI 4 12 #define CK_HSE_DIV2 5 13 14 /* Bus clocks */ 15 #define TIM2 6 16 #define TIM3 7 17 #define TIM4 8 18 #define TIM5 9 19 #define TIM6 10 20 #define TIM7 11 21 #define TIM12 12 22 #define TIM13 13 23 #define TIM14 14 24 #define LPTIM1 15 25 #define SPI2 16 26 #define SPI3 17 27 #define USART2 18 28 #define USART3 19 29 #define UART4 20 30 #define UART5 21 31 #define UART7 22 32 #define UART8 23 33 #define I2C1 24 34 #define I2C2 25 35 #define I2C3 26 36 #define I2C5 27 37 #define SPDIF 28 38 #define CEC 29 39 #define DAC12 30 40 #define MDIO 31 41 #define TIM1 32 42 #define TIM8 33 43 #define TIM15 34 44 #define TIM16 35 45 #define TIM17 36 46 #define SPI1 37 47 #define SPI4 38 48 #define SPI5 39 49 #define USART6 40 50 #define SAI1 41 51 #define SAI2 42 52 #define SAI3 43 53 #define DFSDM 44 54 #define FDCAN 45 55 #define LPTIM2 46 56 #define LPTIM3 47 57 #define LPTIM4 48 58 #define LPTIM5 49 59 #define SAI4 50 60 #define SYSCFG 51 61 #define VREF 52 62 #define TMPSENS 53 63 #define PMBCTRL 54 64 #define HDP 55 65 #define LTDC 56 66 #define DSI 57 67 #define IWDG2 58 68 #define USBPHY 59 69 #define STGENRO 60 70 #define SPI6 61 71 #define I2C4 62 72 #define I2C6 63 73 #define USART1 64 74 #define RTCAPB 65 75 #define TZC 66 76 #define TZPC 67 77 #define IWDG1 68 78 #define BSEC 69 79 #define STGEN 70 80 #define DMA1 71 81 #define DMA2 72 82 #define DMAMUX 73 83 #define ADC12 74 84 #define USBO 75 85 #define SDMMC3 76 86 #define DCMI 77 87 #define CRYP2 78 88 #define HASH2 79 89 #define RNG2 80 90 #define CRC2 81 91 #define HSEM 82 92 #define IPCC 83 93 #define GPIOA 84 94 #define GPIOB 85 95 #define GPIOC 86 96 #define GPIOD 87 97 #define GPIOE 88 98 #define GPIOF 89 99 #define GPIOG 90 100 #define GPIOH 91 101 #define GPIOI 92 102 #define GPIOJ 93 103 #define GPIOK 94 104 #define GPIOZ 95 105 #define CRYP1 96 106 #define HASH1 97 107 #define RNG1 98 108 #define BKPSRAM 99 109 #define MDMA 100 110 #define DMA2D 101 111 #define GPU 102 112 #define ETHCK 103 113 #define ETHTX 104 114 #define ETHRX 105 115 #define ETHMAC 106 116 #define FMC 107 117 #define QSPI 108 118 #define SDMMC1 109 119 #define SDMMC2 110 120 #define CRC1 111 121 #define USBH 112 122 #define ETHSTP 113 123 124 /* Kernel clocks */ 125 #define SDMMC1_K 114 126 #define SDMMC2_K 115 127 #define SDMMC3_K 116 128 #define FMC_K 117 129 #define QSPI_K 118 130 #define ETHMAC_K 119 131 #define RNG1_K 120 132 #define RNG2_K 121 133 #define GPU_K 122 134 #define USBPHY_K 123 135 #define STGEN_K 124 136 #define SPDIF_K 125 137 #define SPI1_K 126 138 #define SPI2_K 127 139 #define SPI3_K 128 140 #define SPI4_K 129 141 #define SPI5_K 130 142 #define SPI6_K 131 143 #define CEC_K 132 144 #define I2C1_K 133 145 #define I2C2_K 134 146 #define I2C3_K 135 147 #define I2C4_K 136 148 #define I2C5_K 137 149 #define I2C6_K 138 150 #define LPTIM1_K 139 151 #define LPTIM2_K 140 152 #define LPTIM3_K 141 153 #define LPTIM4_K 142 154 #define LPTIM5_K 143 155 #define USART1_K 144 156 #define USART2_K 145 157 #define USART3_K 146 158 #define UART4_K 147 159 #define UART5_K 148 160 #define USART6_K 149 161 #define UART7_K 150 162 #define UART8_K 151 163 #define DFSDM_K 152 164 #define FDCAN_K 153 165 #define SAI1_K 154 166 #define SAI2_K 155 167 #define SAI3_K 156 168 #define SAI4_K 157 169 #define ADC12_K 158 170 #define DSI_K 159 171 #define ADFSDM_K 160 172 #define USBO_K 161 173 #define LTDC_K 162 174 175 /* PLL */ 176 #define PLL1 163 177 #define PLL2 164 178 #define PLL3 165 179 #define PLL4 166 180 181 /* ODF */ 182 #define PLL1_P 167 183 #define PLL1_Q 168 184 #define PLL1_R 169 185 #define PLL2_P 170 186 #define PLL2_Q 171 187 #define PLL2_R 172 188 #define PLL3_P 173 189 #define PLL3_Q 174 190 #define PLL3_R 175 191 #define PLL4_P 176 192 #define PLL4_Q 177 193 #define PLL4_R 178 194 195 /* AUX */ 196 #define RTC 179 197 198 /* MCLK */ 199 #define CK_PER 180 200 #define CK_MPU 181 201 #define CK_AXI 182 202 #define CK_MCU 183 203 204 /* Time base */ 205 #define TIM2_K 184 206 #define TIM3_K 185 207 #define TIM4_K 186 208 #define TIM5_K 187 209 #define TIM6_K 188 210 #define TIM7_K 189 211 #define TIM12_K 190 212 #define TIM13_K 191 213 #define TIM14_K 192 214 #define TIM1_K 193 215 #define TIM8_K 194 216 #define TIM15_K 195 217 #define TIM16_K 196 218 #define TIM17_K 197 219 220 /* MCO clocks */ 221 #define CK_MCO1 198 222 #define CK_MCO2 199 223 224 /* TRACE & DEBUG clocks */ 225 #define DBG 200 226 #define CK_DBG 201 227 #define CK_TRACE 202 228 229 /* DDR */ 230 #define DDRC1 203 231 #define DDRC1LP 204 232 #define DDRC2 205 233 #define DDRC2LP 206 234 #define DDRPHYC 207 235 #define DDRPHYCLP 208 236 #define DDRCAPB 209 237 #define DDRCAPBLP 210 238 #define AXIDCG 211 239 #define DDRPHYCAPB 212 240 #define DDRPHYCAPBLP 213 241 #define DDRPERFM 214 242 243 #define STM32MP1_LAST_CLK 215 244