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Searched refs:SAR1_CPU_CORE_MASK (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_plat.h73 #define SAR1_CPU_CORE_MASK 0x00000018 macro
Dmv_ddr_plat.c1219 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in mv_ddr_pre_training_soc_config()
/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h32 #define SAR1_CPU_CORE_MASK 0x00000018 macro
Dddr3_init.c377 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> in ddr3_init_main()