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Searched refs:SCIdx (Results 1 – 11 of 11) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp516 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses() local
517 InstrClassMap[Inst->TheDef] = SCIdx; in collectSchedClasses()
534 unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef); in collectSchedClasses() local
535 if (!SCIdx) { in collectSchedClasses()
540 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
560 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
687 unsigned SCIdx = Pos->second; in createInstRWClass() local
690 if (ClassInstrs[CIdx].first == SCIdx) in createInstRWClass()
695 ClassInstrs[CIdx].first = SCIdx; in createInstRWClass()
728 unsigned SCIdx = SchedClasses.size(); in createInstRWClass() local
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DSubtargetEmitter.cpp1126 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) { in EmitSchedClassTables() local
1127 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()
1128 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1141 if (SCIdx + 1 < SCEnd) in EmitSchedClassTables()
1143 OS << " // #" << SCIdx << '\n'; in EmitSchedClassTables()
DCodeGenSchedule.h420 void inferFromInstRWs(unsigned SCIdx);
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenSchedule.cpp617 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0}); in collectSchedClasses() local
618 InstrClassMap[Inst->TheDef] = SCIdx; in collectSchedClasses()
639 unsigned SCIdx = getSchedClassIdx(*Inst); in collectSchedClasses() local
640 if (!SCIdx) { in collectSchedClasses()
647 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
670 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
793 unsigned SCIdx = Pos->second; in createInstRWClass() local
794 ClassInstrs[SCIdx].push_back(InstDef); in createInstRWClass()
835 unsigned SCIdx = SchedClasses.size(); in createInstRWClass() local
836 SchedClasses.emplace_back(SCIdx, createSchedClassName(InstDefs), nullptr); in createInstRWClass()
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DSubtargetEmitter.cpp1323 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) { in EmitSchedClassTables() local
1324 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()
1325 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1338 << "}, // #" << SCIdx << '\n'; in EmitSchedClassTables()
DCodeGenSchedule.h473 void inferFromInstRWs(unsigned SCIdx);
/external/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp81 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock() local
83 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp86 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock() local
88 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
DAArch64SIMDInstrOpt.cpp228 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst() local
230 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldReplaceInst()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp241 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency() local
242 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx); in computeInstrLatency()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp263 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency() local
264 return capLatency(SchedModel.computeInstrLatency(*STI, SCIdx)); in computeInstrLatency()