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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2001
4  * Denis Peter, MPL AG Switzerland
5  *
6  * Most of these definitions are derived from
7  * linux/drivers/scsi/sym53c8xx_defs.h
8  */
9 
10 #ifndef _SYM53C8XX_DEFS_H
11 #define _SYM53C8XX_DEFS_H
12 
13 
14 #define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
15 
16 #define SCNTL1		0x01    /* no reset                         */
17   #define   ISCON   0x10  /* connected to scsi						*/
18   #define   CRST    0x08  /* force reset                      */
19   #define   IARB    0x02  /* immediate arbitration            */
20 
21 #define SCNTL2		0x02    /* no disconnect expected           */
22 	#define   SDU     0x80  /* cmd: disconnect will raise error */
23 	#define   CHM     0x40  /* sta: chained mode                */
24 	#define   WSS     0x08  /* sta: wide scsi send           [W]*/
25 	#define   WSR     0x01  /* sta: wide scsi received       [W]*/
26 
27 #define SCNTL3		0x03    /* cnf system clock dependent       */
28 	#define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
29 	#define   ULTRA   0x80  /* cmd: ULTRA enable                */
30 				/* bits 0-2, 7 rsvd for C1010       */
31 
32 #define SCID			0x04		/* cnf host adapter scsi address    */
33 	#define   RRE     0x40  /* r/w:e enable response to resel.  */
34 	#define   SRE     0x20  /* r/w:e enable response to select  */
35 
36 #define SXFER			0x05		/* ### Sync speed and count         */
37 				/* bits 6-7 rsvd for C1010          */
38 
39 #define SDID			0x06	/* ### Destination-ID               */
40 
41 #define GPREG			0x07	/* ??? IO-Pins                      */
42 
43 #define SFBR			0x08	/* ### First byte in phase          */
44 
45 #define SOCL			0x09
46 	#define   CREQ	  0x80	/* r/w: SCSI-REQ                    */
47 	#define   CACK	  0x40	/* r/w: SCSI-ACK                    */
48 	#define   CBSY	  0x20	/* r/w: SCSI-BSY                    */
49 	#define   CSEL	  0x10	/* r/w: SCSI-SEL                    */
50 	#define   CATN	  0x08	/* r/w: SCSI-ATN                    */
51 	#define   CMSG	  0x04	/* r/w: SCSI-MSG                    */
52 	#define   CC_D	  0x02	/* r/w: SCSI-C_D                    */
53 	#define   CI_O	  0x01	/* r/w: SCSI-I_O                    */
54 
55 #define SSID			0x0a
56 
57 #define SBCL			0x0b
58 
59 #define DSTAT			0x0c
60   #define   DFE     0x80  /* sta: dma fifo empty              */
61   #define   MDPE    0x40  /* int: master data parity error    */
62   #define   BF      0x20  /* int: script: bus fault           */
63   #define   ABRT    0x10  /* int: script: command aborted     */
64   #define   SSI     0x08  /* int: script: single step         */
65   #define   SIR     0x04  /* int: script: interrupt instruct. */
66   #define   IID     0x01  /* int: script: illegal instruct.   */
67 
68 #define SSTAT0		0x0d
69   #define   ILF     0x80  /* sta: data in SIDL register lsb   */
70   #define   ORF     0x40  /* sta: data in SODR register lsb   */
71   #define   OLF     0x20  /* sta: data in SODL register lsb   */
72   #define   AIP     0x10  /* sta: arbitration in progress     */
73   #define   LOA     0x08  /* sta: arbitration lost            */
74   #define   WOA     0x04  /* sta: arbitration won             */
75   #define   IRST    0x02  /* sta: scsi reset signal           */
76   #define   SDP     0x01  /* sta: scsi parity signal          */
77 
78 #define SSTAT1		0x0e
79 	#define   FF3210  0xf0	/* sta: bytes in the scsi fifo      */
80 
81 #define SSTAT2		0x0f
82   #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
83   #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
84   #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
85   #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
86   #define   LDSC    0x02  /* sta: disconnect & reconnect      */
87 
88 #define DSA				0x10		/* --> Base page                    */
89 #define DSA1			0x11
90 #define DSA2			0x12
91 #define DSA3			0x13
92 
93 #define ISTAT			0x14	/* --> Main Command and status      */
94   #define   CABRT   0x80  /* cmd: abort current operation     */
95   #define   SRST    0x40  /* mod: reset chip                  */
96   #define   SIGP    0x20  /* r/w: message from host to ncr    */
97   #define   SEM     0x10  /* r/w: message between host + ncr  */
98   #define   CON     0x08  /* sta: connected to scsi           */
99   #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
100   #define   SIP     0x02  /* sta: scsi-interrupt              */
101   #define   DIP     0x01  /* sta: host/script interrupt       */
102 
103 
104 #define CTEST0		0x18
105 #define CTEST1		0x19
106 #define CTEST2		0x1a
107 	#define   CSIGP   0x40
108 				/* bits 0-2,7 rsvd for C1010        */
109 
110 #define CTEST3		0x1b
111 	#define   FLF     0x08  /* cmd: flush dma fifo              */
112 	#define   CLF		0x04	/* cmd: clear dma fifo		    */
113 	#define   FM      0x02  /* mod: fetch pin mode              */
114 	#define   WRIE    0x01  /* mod: write and invalidate enable */
115 				/* bits 4-7 rsvd for C1010          */
116 
117 #define DFIFO			0x20
118 #define CTEST4		0x21
119 	#define   BDIS    0x80  /* mod: burst disable               */
120 	#define   MPEE    0x08  /* mod: master parity error enable  */
121 
122 #define CTEST5		0x22
123 	#define   DFS     0x20  /* mod: dma fifo size               */
124 				/* bits 0-1, 3-7 rsvd for C1010          */
125 #define CTEST6		0x23
126 
127 #define DBC				0x24	/* ### Byte count and command       */
128 #define DNAD			0x28	/* ### Next command register        */
129 #define DSP				0x2c	/* --> Script Pointer               */
130 #define DSPS			0x30	/* --> Script pointer save/opcode#2 */
131 
132 #define SCRATCHA	0x34  /* Temporary register a            */
133 #define SCRATCHA1	0x35
134 #define SCRATCHA2	0x36
135 #define SCRATCHA3	0x37
136 
137 #define DMODE			0x38
138 	#define   BL_2    0x80  /* mod: burst length shift value +2 */
139 	#define   BL_1    0x40  /* mod: burst length shift value +1 */
140 	#define   ERL     0x08  /* mod: enable read line            */
141 	#define   ERMP    0x04  /* mod: enable read multiple        */
142 	#define   BOF     0x02  /* mod: burst op code fetch         */
143 	#define   MAN     0x01  /* mod: manual start				         */
144 
145 #define DIEN		0x39
146 #define SBR			0x3a
147 
148 #define DCNTL		0x3b			/* --> Script execution control     */
149 	#define   CLSE    0x80  /* mod: cache line size enable      */
150 	#define   PFF     0x40  /* cmd: pre-fetch flush             */
151 	#define   PFEN    0x20  /* mod: pre-fetch enable            */
152 	#define   SSM     0x10  /* mod: single step mode            */
153 	#define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
154 	#define   STD     0x04  /* cmd: start dma mode              */
155 	#define   IRQD    0x02  /* mod: irq disable                 */
156 	#define	  NOCOM   0x01	/* cmd: protect sfbr while reselect */
157 				/* bits 0-1 rsvd for C1010          */
158 
159 #define ADDER			0x3c
160 
161 #define SIEN			0x40	/* -->: interrupt enable            */
162 #define SIST			0x42	/* <--: interrupt status            */
163   #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
164   #define   STO     0x0400/* sta: timeout (select)            */
165   #define   GEN     0x0200/* sta: timeout (general)           */
166   #define   HTH     0x0100/* sta: timeout (handshake)         */
167   #define   MA      0x80  /* sta: phase mismatch              */
168   #define   CMP     0x40  /* sta: arbitration complete        */
169   #define   SEL     0x20  /* sta: selected by another device  */
170   #define   RSL     0x10  /* sta: reselected by another device*/
171   #define   SGE     0x08  /* sta: gross error (over/underflow)*/
172   #define   UDC     0x04  /* sta: unexpected disconnect       */
173   #define   RST     0x02  /* sta: scsi bus reset detected     */
174   #define   PAR     0x01  /* sta: scsi parity error           */
175 
176 #define SLPAR				0x44
177 #define SWIDE				0x45
178 #define MACNTL			0x46
179 #define GPCNTL			0x47
180 #define STIME0			0x48    /* cmd: timeout for select&handshake*/
181 #define STIME1			0x49    /* cmd: timeout user defined        */
182 #define RESPID			0x4a    /* sta: Reselect-IDs                */
183 
184 #define STEST0			0x4c
185 
186 #define STEST1			0x4d
187 	#define   SCLK    0x80	/* Use the PCI clock as SCSI clock	*/
188 	#define   DBLEN   0x08	/* clock doubler running		*/
189 	#define   DBLSEL  0x04	/* clock doubler selected		*/
190 
191 
192 #define STEST2			0x4e
193 	#define   ROF     0x40	/* reset scsi offset (after gross error!) */
194 	#define   EXT     0x02  /* extended filtering                     */
195 
196 #define STEST3			0x4f
197 	#define   TE     0x80	/* c: tolerAnt enable */
198 	#define   HSC    0x20	/* c: Halt SCSI Clock */
199 	#define   CSF    0x02	/* c: clear scsi fifo */
200 
201 #define SIDL			0x50	/* Lowlevel: latched from scsi data */
202 #define STEST4		0x52
203 	#define SMODE	0xc0	/* SCSI bus mode      (895/6 only) */
204 	#define SMODE_HVD 0x40	/* High Voltage Differential       */
205 	#define SMODE_SE  0x80	/* Single Ended                    */
206 	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
207 	#define LCKFRQ 0x20	/* Frequency Lock (895/6 only)     */
208 				/* bits 0-5 rsvd for C1010          */
209 
210 #define SODL			0x54	/* Lowlevel: data out to scsi data  */
211 
212 #define SBDL			0x58	/* Lowlevel: data from scsi data    */
213 
214 
215 /*-----------------------------------------------------------
216 **
217 **	Utility macros for the script.
218 **
219 **-----------------------------------------------------------
220 */
221 
222 #define REG(r) (r)
223 
224 /*-----------------------------------------------------------
225 **
226 **	SCSI phases
227 **
228 **	DT phases illegal for ncr driver.
229 **
230 **-----------------------------------------------------------
231 */
232 
233 #define	SCR_DATA_OUT	0x00000000
234 #define	SCR_DATA_IN	0x01000000
235 #define	SCR_COMMAND	0x02000000
236 #define	SCR_STATUS	0x03000000
237 #define SCR_DT_DATA_OUT	0x04000000
238 #define SCR_DT_DATA_IN	0x05000000
239 #define SCR_MSG_OUT	0x06000000
240 #define SCR_MSG_IN      0x07000000
241 
242 #define SCR_ILG_OUT	0x04000000
243 #define SCR_ILG_IN	0x05000000
244 
245 /*-----------------------------------------------------------
246 **
247 **	Data transfer via SCSI.
248 **
249 **-----------------------------------------------------------
250 **
251 **	MOVE_ABS (LEN)
252 **	<<start address>>
253 **
254 **	MOVE_IND (LEN)
255 **	<<dnad_offset>>
256 **
257 **	MOVE_TBL
258 **	<<dnad_offset>>
259 **
260 **-----------------------------------------------------------
261 */
262 
263 #define OPC_MOVE          0x08000000
264 
265 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
266 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
267 #define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
268 
269 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
270 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
271 #define SCR_CHMOV_TBL     (0x10000000)
272 
273 
274 /*-----------------------------------------------------------
275 **
276 **	Selection
277 **
278 **-----------------------------------------------------------
279 **
280 **	SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
281 **	<<alternate_address>>
282 **
283 **	SEL_TBL | << dnad_offset>>  [ | REL_JMP]
284 **	<<alternate_address>>
285 **
286 **-----------------------------------------------------------
287 */
288 
289 #define	SCR_SEL_ABS	0x40000000
290 #define	SCR_SEL_ABS_ATN	0x41000000
291 #define	SCR_SEL_TBL	0x42000000
292 #define	SCR_SEL_TBL_ATN	0x43000000
293 
294 
295 #define SCR_JMP_REL     0x04000000
296 #define SCR_ID(id)	(((unsigned long)(id)) << 16)
297 
298 /*-----------------------------------------------------------
299 **
300 **	Waiting for Disconnect or Reselect
301 **
302 **-----------------------------------------------------------
303 **
304 **	WAIT_DISC
305 **	dummy: <<alternate_address>>
306 **
307 **	WAIT_RESEL
308 **	<<alternate_address>>
309 **
310 **-----------------------------------------------------------
311 */
312 
313 #define	SCR_WAIT_DISC	0x48000000
314 #define SCR_WAIT_RESEL  0x50000000
315 
316 /*-----------------------------------------------------------
317 **
318 **	Bit Set / Reset
319 **
320 **-----------------------------------------------------------
321 **
322 **	SET (flags {|.. })
323 **
324 **	CLR (flags {|.. })
325 **
326 **-----------------------------------------------------------
327 */
328 
329 #define SCR_SET(f)     (0x58000000 | (f))
330 #define SCR_CLR(f)     (0x60000000 | (f))
331 
332 #define	SCR_CARRY	0x00000400
333 #define	SCR_TRG		0x00000200
334 #define	SCR_ACK		0x00000040
335 #define	SCR_ATN		0x00000008
336 
337 
338 /*-----------------------------------------------------------
339 **
340 **	Memory to memory move
341 **
342 **-----------------------------------------------------------
343 **
344 **	COPY (bytecount)
345 **	<< source_address >>
346 **	<< destination_address >>
347 **
348 **	SCR_COPY   sets the NO FLUSH option by default.
349 **	SCR_COPY_F does not set this option.
350 **
351 **	For chips which do not support this option,
352 **	ncr_copy_and_bind() will remove this bit.
353 **-----------------------------------------------------------
354 */
355 
356 #define SCR_NO_FLUSH 0x01000000
357 
358 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
359 #define SCR_COPY_F(n) (0xc0000000 | (n))
360 
361 /*-----------------------------------------------------------
362 **
363 **	Register move and binary operations
364 **
365 **-----------------------------------------------------------
366 **
367 **	SFBR_REG (reg, op, data)        reg  = SFBR op data
368 **	<< 0 >>
369 **
370 **	REG_SFBR (reg, op, data)        SFBR = reg op data
371 **	<< 0 >>
372 **
373 **	REG_REG  (reg, op, data)        reg  = reg op data
374 **	<< 0 >>
375 **
376 **-----------------------------------------------------------
377 **	On 810A, 860, 825A, 875, 895 and 896 chips the content
378 **	of SFBR register can be used as data (SCR_SFBR_DATA).
379 **	The 896 has additionnal IO registers starting at
380 **	offset 0x80. Bit 7 of register offset is stored in
381 **	bit 7 of the SCRIPTS instruction first DWORD.
382 **-----------------------------------------------------------
383 */
384 
385 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
386 
387 #define SCR_SFBR_REG(reg,op,data) \
388 	(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
389 
390 #define SCR_REG_SFBR(reg,op,data) \
391 	(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
392 
393 #define SCR_REG_REG(reg,op,data) \
394 	(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
395 
396 
397 #define      SCR_LOAD   0x00000000
398 #define      SCR_SHL    0x01000000
399 #define      SCR_OR     0x02000000
400 #define      SCR_XOR    0x03000000
401 #define      SCR_AND    0x04000000
402 #define      SCR_SHR    0x05000000
403 #define      SCR_ADD    0x06000000
404 #define      SCR_ADDC   0x07000000
405 
406 #define      SCR_SFBR_DATA   (0x00800000>>8ul)	/* Use SFBR as data */
407 
408 /*-----------------------------------------------------------
409 **
410 **	FROM_REG (reg)		  SFBR = reg
411 **	<< 0 >>
412 **
413 **	TO_REG	 (reg)		  reg  = SFBR
414 **	<< 0 >>
415 **
416 **	LOAD_REG (reg, data)	  reg  = <data>
417 **	<< 0 >>
418 **
419 **	LOAD_SFBR(data)		  SFBR = <data>
420 **	<< 0 >>
421 **
422 **-----------------------------------------------------------
423 */
424 
425 #define	SCR_FROM_REG(reg) \
426 	SCR_REG_SFBR(reg,SCR_OR,0)
427 
428 #define	SCR_TO_REG(reg) \
429 	SCR_SFBR_REG(reg,SCR_OR,0)
430 
431 #define	SCR_LOAD_REG(reg,data) \
432 	SCR_REG_REG(reg,SCR_LOAD,data)
433 
434 #define SCR_LOAD_SFBR(data) \
435 	(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
436 
437 /*-----------------------------------------------------------
438 **
439 **	LOAD  from memory   to register.
440 **	STORE from register to memory.
441 **
442 **	Only supported by 810A, 860, 825A, 875, 895 and 896.
443 **
444 **-----------------------------------------------------------
445 **
446 **	LOAD_ABS (LEN)
447 **	<<start address>>
448 **
449 **	LOAD_REL (LEN)        (DSA relative)
450 **	<<dsa_offset>>
451 **
452 **-----------------------------------------------------------
453 */
454 
455 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
456 #define SCR_NO_FLUSH2	0x02000000
457 #define SCR_DSA_REL2	0x10000000
458 
459 #define SCR_LOAD_R(reg, how, n) \
460 	(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
461 
462 #define SCR_STORE_R(reg, how, n) \
463 	(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
464 
465 #define SCR_LOAD_ABS(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
466 #define SCR_LOAD_REL(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
467 #define SCR_LOAD_ABS_F(reg, n)	SCR_LOAD_R(reg, 0, n)
468 #define SCR_LOAD_REL_F(reg, n)	SCR_LOAD_R(reg, SCR_DSA_REL2, n)
469 
470 #define SCR_STORE_ABS(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
471 #define SCR_STORE_REL(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
472 #define SCR_STORE_ABS_F(reg, n)	SCR_STORE_R(reg, 0, n)
473 #define SCR_STORE_REL_F(reg, n)	SCR_STORE_R(reg, SCR_DSA_REL2, n)
474 
475 
476 /*-----------------------------------------------------------
477 **
478 **	Waiting for Disconnect or Reselect
479 **
480 **-----------------------------------------------------------
481 **
482 **	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
483 **	<<address>>
484 **
485 **	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
486 **	<<distance>>
487 **
488 **	CALL            [ | IFTRUE/IFFALSE ( ... ) ]
489 **	<<address>>
490 **
491 **	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
492 **	<<distance>>
493 **
494 **	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
495 **	<<dummy>>
496 **
497 **	INT             [ | IFTRUE/IFFALSE ( ... ) ]
498 **	<<ident>>
499 **
500 **	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
501 **	<<ident>>
502 **
503 **	Conditions:
504 **	     WHEN (phase)
505 **	     IF   (phase)
506 **	     CARRYSET
507 **	     DATA (data, mask)
508 **
509 **-----------------------------------------------------------
510 */
511 
512 #define SCR_NO_OP       0x80000000
513 #define SCR_JUMP        0x80080000
514 #define SCR_JUMP64      0x80480000
515 #define SCR_JUMPR       0x80880000
516 #define SCR_CALL        0x88080000
517 #define SCR_CALLR       0x88880000
518 #define SCR_RETURN      0x90080000
519 #define SCR_INT         0x98080000
520 #define SCR_INT_FLY     0x98180000
521 
522 #define IFFALSE(arg)   (0x00080000 | (arg))
523 #define IFTRUE(arg)    (0x00000000 | (arg))
524 
525 #define WHEN(phase)    (0x00030000 | (phase))
526 #define IF(phase)      (0x00020000 | (phase))
527 
528 #define DATA(D)        (0x00040000 | ((D) & 0xff))
529 #define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
530 
531 #define CARRYSET       (0x00200000)
532 
533 
534 #define SIR_COMPLETE					 0x10000000
535 /* script errors */
536 #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
537 #define SIR_CMD_OUT_ILL_PH     0x00000002
538 #define SIR_STATUS_ILL_PH			 0x00000003
539 #define SIR_MSG_RECEIVED			 0x00000004
540 #define SIR_DATA_IN_ERR        0x00000005
541 #define SIR_DATA_OUT_ERR			 0x00000006
542 #define SIR_SCRIPT_ERROR			 0x00000007
543 #define SIR_MSG_OUT_NO_CMD		 0x00000008
544 #define SIR_MSG_OVER7					 0x00000009
545 /* Fly interrupt */
546 #define INT_ON_FY							 0x00000080
547 
548 /* Hardware errors  are defined in scsi.h */
549 
550 #define SCSI_IDENTIFY					0xC0
551 
552 #endif
553