Searched refs:SCVTF (Results 1 – 13 of 13) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 26 # SCVTF on fixed point W-registers is undefined if scale<5> == 0.
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 26 # SCVTF on fixed point W-registers is undefined if scale<5> == 0.
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1504 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator
1505 SCVTF_hw = SCVTF | FP16,
1506 SCVTF_hx = SCVTF | SixtyFourBits | FP16,
1507 SCVTF_sw = SCVTF,
1508 SCVTF_sx = SCVTF | SixtyFourBits,
1509 SCVTF_dw = SCVTF | FP64,
1510 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
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| D | disasm-aarch64.cc | 2499 FORMAT(SCVTF, "scvtf") in VisitNEON2RegMiscFP16()
3970 FORMAT(SCVTF, "scvtf") in VisitNEONScalar2RegMiscFP16()
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| D | assembler-aarch64.cc | 3090 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd)); in scvtf()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1281 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator
1282 SCVTF_sw = SCVTF,
1283 SCVTF_sx = SCVTF | SixtyFourBits,
1284 SCVTF_dw = SCVTF | FP64,
1285 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
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| D | assembler-arm64.cc | 3221 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd)); in scvtf()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 115 #define SCVTF 0x9e620000 macro
1399 FAIL_IF(push_inst(compiler, (SCVTF ^ inv_bits) | VD(dst_r) | RN(src))); in sljit_emit_fop1_conv_f64_from_sw()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 573 // SCVTF,UCVTF V,V
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| D | AArch64InstrInfo.td | 2555 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2884 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
3366 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;
4680 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
4754 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
4925 // SCVTF GPR -> FPR is 9 cycles.
4926 // SCVTF FPR -> FPR is 4 cyclces.
4928 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4980 // SCVTF on floating point registers (both source and destination
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 575 // SCVTF,UCVTF V,V
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| D | AArch64InstrInfo.td | 2836 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
3148 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
3643 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;
5015 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
5124 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
5295 // SCVTF GPR -> FPR is 9 cycles.
5296 // SCVTF FPR -> FPR is 4 cyclces.
5298 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
5350 // SCVTF on floating point registers (both source and destination
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2882 ### SCVTF ### subsection
2889 ### SCVTF ### subsection
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