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Searched refs:SC_RSTCTRL (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/mach-uniphier/clk/
Dclk-dram-ld4.c19 tmp = readl(SC_RSTCTRL); in uniphier_ld4_dram_clk_init()
21 writel(tmp, SC_RSTCTRL); in uniphier_ld4_dram_clk_init()
22 readl(SC_RSTCTRL); /* dummy read */ in uniphier_ld4_dram_clk_init()
Dclk-ld4.c18 tmp = readl(SC_RSTCTRL); in uniphier_ld4_clk_init()
22 writel(tmp, SC_RSTCTRL); in uniphier_ld4_clk_init()
23 readl(SC_RSTCTRL); /* dummy read */ in uniphier_ld4_clk_init()
Dclk-pro5.c16 tmp = readl(SC_RSTCTRL); in uniphier_pro5_clk_init()
23 writel(tmp, SC_RSTCTRL); in uniphier_pro5_clk_init()
24 readl(SC_RSTCTRL); /* dummy read */ in uniphier_pro5_clk_init()
Dclk-pro4.c18 tmp = readl(SC_RSTCTRL); in uniphier_pro4_clk_init()
26 writel(tmp, SC_RSTCTRL); in uniphier_pro4_clk_init()
27 readl(SC_RSTCTRL); /* dummy read */ in uniphier_pro4_clk_init()
Dclk-pxs2.c17 tmp = readl(SC_RSTCTRL); in uniphier_pxs2_clk_init()
24 writel(tmp, SC_RSTCTRL); in uniphier_pxs2_clk_init()
25 readl(SC_RSTCTRL); /* dummy read */ in uniphier_pxs2_clk_init()
Dclk-early-ld4.c20 tmp = readl(SC_RSTCTRL); in uniphier_ld4_early_clk_init()
22 writel(tmp, SC_RSTCTRL); in uniphier_ld4_early_clk_init()
/external/u-boot/arch/arm/mach-uniphier/
Dsc64-regs.h14 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) macro
Dsc-regs.h41 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) macro