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Searched refs:SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dwrap_sdram_config.c35 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dsdram_gen5.h249 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 macro