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Searched refs:SDR_PHYGRP_RWMGRGRP_ADDRESS (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/altera/
Dsequencer.c14 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
17 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
246 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS | in set_rank_and_odt_mask()
813 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()
830 SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()
848 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_init_load_regs()
879 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_load_user()
941 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_initialize()
1130 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_write_test_issue()
1154 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_write_test_issue()
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Dsequencer.h85 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) macro