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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h83 DenseMap<SDValue, SDValue> PromotedIntegers;
87 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
91 DenseMap<SDValue, SDValue> SoftenedFloats;
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats;
99 DenseMap<SDValue, SDValue> ScalarizedVectors;
103 DenseMap<SDValue, std::pair<SDValue, SDValue> > SplitVectors;
107 DenseMap<SDValue, SDValue> WidenedVectors;
111 DenseMap<SDValue, SDValue> ReplacedValues;
135 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
140 void AnalyzeNewValue(SDValue &Val);
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h97 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
101 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
105 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
109 SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;
113 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
117 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
121 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
125 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
129 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
152 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h103 SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
104 SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
146 TableId getTableId(SDValue V) { in getTableId()
165 const SDValue &getSDValue(TableId &Id) { in getSDValue()
186 TableId NewId = getTableId(SDValue(New, i)); in NoteDeletion()
187 TableId OldId = getTableId(SDValue(Old, i)); in NoteDeletion()
193 ValueToIdMap.erase(SDValue(Old, i)); in NoteDeletion()
210 void AnalyzeNewValue(SDValue &Val);
213 void RemapValue(SDValue &V);
216 SDValue BitConvertToInteger(SDValue Op);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h115 bool IsEligibleForTailCallOptimization(SDValue Callee,
118 const SmallVectorImpl<SDValue> &OutVals,
148 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
149 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
154 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h36 unsigned getMSACtrlReg(const SDValue RegIdx) const;
46 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
47 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
51 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
52 SDValue &Offset) const override;
54 bool selectAddrDefault(SDValue Addr, SDValue &Base,
55 SDValue &Offset) const override;
57 bool selectIntAddr(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const override;
60 bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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DMipsISelDAGToDAG.h59 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
60 SDValue &Offset) const;
63 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
64 SDValue &Offset) const;
67 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
68 SDValue &Offset) const;
70 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
73 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp77 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
78 SDValue &Offset) const { in selectAddrRegImm()
83 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
84 SDValue &Offset) const { in selectAddrDefault()
89 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
90 SDValue &Offset) const { in selectIntAddr()
95 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, in selectIntAddr11MM()
96 SDValue &Offset) const { in selectIntAddr11MM()
101 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, in selectIntAddr12MM()
102 SDValue &Offset) const { in selectIntAddr12MM()
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h34 unsigned getMSACtrlReg(const SDValue RegIdx) const;
42 void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
45 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
46 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
49 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
50 SDValue &Offset) const override;
52 bool selectAddrDefault(SDValue Addr, SDValue &Base,
53 SDValue &Offset) const override;
55 bool selectIntAddr(SDValue Addr, SDValue &Base,
56 SDValue &Offset) const override;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
61 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
62 SDValue &Offset) const;
65 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
66 SDValue &Offset) const;
68 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
69 SDValue &Offset) const;
71 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
72 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp69 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
70 SDValue &Offset) const { in selectAddrRegImm()
75 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
76 SDValue &Offset) const { in selectAddrDefault()
81 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
82 SDValue &Offset) const { in selectIntAddr()
87 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, in selectIntAddr11MM()
88 SDValue &Offset) const { in selectIntAddr11MM()
93 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, in selectIntAddr12MM()
94 SDValue &Offset) const { in selectIntAddr12MM()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h146 SDValue Root;
249 const SDValue &getRoot() const { return Root; }
253 SDValue getEntryNode() const {
254 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
259 const SDValue &setRoot(SDValue N) {
325 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
326 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
327 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
328 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
329 SDValue getTargetConstant(uint64_t Val, EVT VT) {
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h192 SDValue Root;
287 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
376 const SDValue &getRoot() const { return Root; }
379 SDValue getEntryNode() const {
380 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
385 const SDValue &setRoot(SDValue N) {
477 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
479 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
481 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
483 SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
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DSelectionDAGTargetInfo.h49 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
50 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
56 return SDValue(); in EmitTargetCodeForMemcpy()
65 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
66 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove()
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
69 return SDValue(); in EmitTargetCodeForMemmove()
78 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemset()
79 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.h233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
254 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
255 SDValue &Offset,
262 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
268 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
273 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
279 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
290 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
293 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h52 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
53 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
54 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
59 return SDValue(); in EmitTargetCodeForMemcpy()
68 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
69 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove()
70 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
72 return SDValue(); in EmitTargetCodeForMemmove()
81 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemset()
82 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset()
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DSelectionDAG.h243 SDValue Root;
364 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals);
454 const SDValue &getRoot() const { return Root; }
457 SDValue getEntryNode() const {
458 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
463 const SDValue &setRoot(SDValue N) {
556 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
558 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
561 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
567 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h31 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32 const SDValue &InitPtr,
33 SDValue Chain,
35 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.h486 bool isZeroNode(SDValue Elt);
517 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
558 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
563 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
567 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
579 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
596 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
605 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
611 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
628 virtual void LowerAsmOperandForConstraint(SDValue Op,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h37 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
40 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
41 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
46 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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DSIISelLowering.h41 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
42 SDValue Chain, uint64_t Offset) const;
43 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
44 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
45 const SDLoc &SL, SDValue Chain,
49 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
50 const SDLoc &SL, SDValue Chain,
52 SDValue getPreloadedValue(SelectionDAG &DAG,
57 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
59 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h449 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
519 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
520 SDValue &Offset,
527 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
534 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
539 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
546 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
551 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
554 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
555 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.h541 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
595 bool hasAndNotCompare(SDValue) const override { in hasAndNotCompare() argument
627 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
628 SDValue &Offset,
635 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
642 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
647 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
654 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
659 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
662 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
147 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
151 SmallVectorImpl<SDValue> &InVals) const;
152 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
156 const SmallVectorImpl<SDValue> &OutVals,
159 SmallVectorImpl<SDValue> &InVals) const;
160 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
161 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
148 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
152 SmallVectorImpl<SDValue> &InVals) const;
153 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
157 const SmallVectorImpl<SDValue> &OutVals,
160 SmallVectorImpl<SDValue> &InVals) const;
161 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
162 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h253 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
258 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
270 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
274 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
299 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
322 bool isZExtFree(SDValue Val, EVT VT2) const override;
446 bool hasAndNotCompare(SDValue V) const override { in hasAndNotCompare()
451 bool hasAndNot(SDValue Y) const override { in hasAndNot()
528 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
532 SmallVectorImpl<SDValue> &InVals) const override;
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