| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 77 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
88 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
89 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
90 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
91 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
92 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
93 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
94 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
95 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
96 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
97 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
98 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
99 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
100 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
102 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
103 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
104 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86TargetTransformInfo.cpp | 887 { ISD::SETCC, MVT::v2i64, 8 }, in getCmpSelInstrCost()
888 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
889 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
890 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
894 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
895 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
896 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
900 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
901 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
903 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
94 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
95 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
96 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
97 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
98 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
99 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
100 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
101 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
102 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86TargetTransformInfo.cpp | 1522 { ISD::SETCC, MVT::v2i64, 8 }, in getCmpSelInstrCost()
1523 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
1524 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
1525 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
1529 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
1530 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
1531 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
1535 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
1536 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
1538 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | aarch64-neon-v1i1-setcc.ll | 4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
8 ; operands of SETCC have been legalized.
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-neon-v1i1-setcc.ll | 4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
8 ; operands of SETCC have been legalized.
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 4 ** DONE Problem with asymmetric SETCC operations
96 ** Create test case for each Illegal SETCC case
97 The DAG combiner may someimes produce illegal i16 SETCC instructions.
99 *** TODO SETCC (ctlz x), 5) == const
100 *** TODO SETCC (and load, const) == const
101 *** DONE SETCC (zext x) == const
102 *** TODO SETCC (sext x) == const
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | sdiv-minsigned.ll | 4 ; This checks for a bug in the DAG combiner where a SETCC was created with
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 165 case ISD::SETCC: in LegalizeOp()
223 else if (Node->getOpcode() == ISD::SETCC) in LegalizeOp()
361 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), in UnrollVSETCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | int-cmp-54.ll | 1 ; Check that custom handling of SETCC does not crash
|
| D | setcc-03.ll | 1 ; Test SETCC with an i32 result for every integer condition.
|
| D | setcc-01.ll | 1 ; Test SETCC for every integer condition. The tests here assume that
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 94 setOperationAction(ISD::SETCC, MVT::i1, Custom); in PTXTargetLowering()
113 case ISD::SETCC: in LowerOperation()
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2); in LowerSETCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | avx512-adc-sbb.ll | 4 ; This asserted because we didn't account for a zext of a non-SETCC node:
|
| D | avx512-vec3-crash.ll | 4 ; This test crashed during type legalization of SETCC result type.
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| D | promote-setcc.ll | 3 ; The DAG combiner may sometimes create illegal i16 SETCC operations when run
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
337 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
430 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_SETCC()
481 case ISD::SETCC: in ScalarizeVectorOperand()
577 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecOp_VSETCC()
671 case ISD::SETCC: in SplitVectorResult()
1598 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
2213 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
2214 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
2279 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 117 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SystemZTargetLowering()
118 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SystemZTargetLowering()
119 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SystemZTargetLowering()
120 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SystemZTargetLowering()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 344 SETCC, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.h | 42 SETCC, enumerator
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | setcc-01.ll | 1 ; Test SETCC for every integer condition. The tests here assume that
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.h | 42 SETCC, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
|