| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | unsupported-cc.ll | 56 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
91 ; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x
105 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
|
| D | setcc.ll | 162 ; R600: SETGT
190 ; R600: SETGT
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | unsupported-cc.ll | 56 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
91 ; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x
105 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
|
| D | setcc.ll | 156 ; R600: SETGT
184 ; R600: SETGT
|
| D | sdiv.ll | 10 ; selectcc Remainder -1, 0, -1, SETGT
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 156 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; in getFCmpCondCode()
164 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; in getFCmpCondCode()
194 case ICmpInst::ICMP_SGT: return ISD::SETGT; in getICmpCondCode()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 733 SETGT, // 1 X 0 1 0 True if greater than enumerator
746 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 871 SETGT, // 1 X 0 1 0 True if greater than enumerator
884 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 934 SETGT, // 1 X 0 1 0 True if greater than enumerator
947 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 25 IntRegs:$fval, SETGT)),
102 DoubleRegs:$fval, SETGT)),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 561 case ISD::SETGT: return PPC::PRED_GT; in getPredicateForSetCC()
586 case ISD::SETGT: return 1; // Bit #1 = SETOGT in getCRIdxForSetCC()
641 case ISD::SETGT: { in SelectSETCC()
678 case ISD::SETGT: { in SelectSETCC()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 190 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
209 case ICmpInst::ICMP_SGT: return ISD::SETGT; in getICmpCondCode()
|
| D | TargetLoweringBase.cpp | 783 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
784 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
785 CCs[RTLIB::OGT_F128] = ISD::SETGT; in InitCmpLibcallCCs()
786 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in InitCmpLibcallCCs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 189 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
208 case ICmpInst::ICMP_SGT: return ISD::SETGT; in getICmpCondCode()
|
| D | TargetLoweringBase.cpp | 517 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
518 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
519 CCs[RTLIB::OGT_F128] = ISD::SETGT; in InitCmpLibcallCCs()
520 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in InitCmpLibcallCCs()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 50 defm GT_S : ComparisonInt<SETGT, "gt_s">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 48 defm GT_S : ComparisonInt<SETGT, "gt_s", 0x4a, 0x55>;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 535 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
536 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
2088 case ISD::SETGT: in SimplifySetCC()
2244 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); in SimplifySetCC()
2259 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
2265 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
2277 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
2298 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); in SimplifySetCC()
2546 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2808 case ISD::SETGT: { in get32BitZExtCompare()
2989 case ISD::SETGT: { in get32BitSExtCompare()
3146 case ISD::SETGT: { in get64BitZExtCompare()
3307 case ISD::SETGT: { in get64BitSExtCompare()
3634 case ISD::SETGT: in SelectCC()
3661 case ISD::SETGT: in SelectCC()
3697 case ISD::SETGT: return PPC::PRED_GT; in getPredicateForSetCC()
3718 case ISD::SETGT: return 1; // Bit #1 = SETOGT in getCRIdxForSetCC()
3752 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
3776 case ISD::SETGT: in getVCmpInst()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2106 case ISD::SETGT: return PPC::PRED_GT; in getPredicateForSetCC()
2127 case ISD::SETGT: return 1; // Bit #1 = SETOGT in getCRIdxForSetCC()
2161 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
2185 case ISD::SETGT: in getVCmpInst()
2207 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
2216 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break; in getVCmpInst()
2233 case ISD::SETGT: in getVCmpInst()
2298 case ISD::SETGT: { in trySETCC()
2341 case ISD::SETGT: { in trySETCC()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 191 case ISD::SETGT: in softenSetCCOperands()
1583 case ISD::SETGT: in SimplifySetCC()
1752 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1782 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1788 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1800 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1821 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); in SimplifySetCC()
2142 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
3136 ISD::SETGT); in expandFP_TO_SINT()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 199 case ISD::SETGT: in kill()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 680 case ISD::SETGT: in EmitInstrWithCustomInserter()
715 bool isSignedCmp = (CC == ISD::SETGT || in EmitInstrWithCustomInserter()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 96 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
140 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 317 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: in Select()
|