/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 727 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator 752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 865 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator 890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 928 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator 953 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | Analysis.cpp | 167 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; in getFCmpCondCode() 189 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
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/external/llvm/lib/CodeGen/ |
D | Analysis.cpp | 177 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode() 189 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN() 204 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | Analysis.cpp | 176 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode() 188 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN() 203 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaISelDAGToDAG.cpp | 315 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: in Select() 336 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: in Select()
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | README.txt | 79 SETULE unimplemented
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonSelectCCInfo.td | 54 IntRegs:$fval, SETULE)),
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrInteger.td | 49 defm LE_U : ComparisonInt<SETULE, "le_u">;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrInteger.td | 51 defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | TargetLowering.cpp | 233 case ISD::SETULE: in softenSetCCOperands() 1581 case ISD::SETULE: in SimplifySetCC() 1603 case ISD::SETULE: { in SimplifySetCC() 1763 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC() 1784 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC() 1877 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC() 1878 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC() 1889 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC() 1950 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC() 2156 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SIInsertSkips.cpp | 236 case ISD::SETULE: in kill()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 489 case ISD::SETULE: in NegateCC() 707 case ISD::SETULE: in EmitInstrWithCustomInserter()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | TargetLowering.cpp | 238 case ISD::SETULE: in softenSetCCOperands() 1891 } else if (Cond == ISD::CondCode::SETULE) { in optimizeSetCCOfSignedTruncationCheck() 2177 case ISD::SETULE: in SimplifySetCC() 2200 case ISD::SETULE: { in SimplifySetCC() 2375 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC() 2509 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC() 2510 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC() 2521 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC() 2591 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC() 2793 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCISelDAGToDAG.cpp | 2869 case ISD::SETULE: { in get32BitZExtCompare() 3042 case ISD::SETULE: { in get32BitSExtCompare() 3201 case ISD::SETULE: { in get64BitZExtCompare() 3364 case ISD::SETULE: { in get64BitSExtCompare() 3639 case ISD::SETULE: in SelectCC() 3666 case ISD::SETULE: in SelectCC() 3694 case ISD::SETULE: in getPredicateForSetCC() 3724 case ISD::SETULE: in getCRIdxForSetCC() 3755 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst() 3763 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst() [all …]
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D | PPCInstrQPX.td | 1016 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULE), 1063 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULE), 1123 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULE)), 1144 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULE)), 1165 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULE)),
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D | PPCInstrInfo.td | 3255 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3509 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3537 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3577 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3605 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3633 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3664 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3695 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)), 3729 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3756 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrQPX.td | 1016 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULE), 1063 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULE), 1123 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULE)), 1144 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULE)), 1165 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULE)),
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D | PPCISelDAGToDAG.cpp | 2103 case ISD::SETULE: in getPredicateForSetCC() 2133 case ISD::SETULE: in getCRIdxForSetCC() 2164 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst() 2172 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst() 2208 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst() 2217 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
D | PTXInstrInfo.td | 550 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">; 563 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">; 576 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">; 589 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">; 598 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">;
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | TargetLowering.cpp | 2086 case ISD::SETULE: in SimplifySetCC() 2108 case ISD::SETULE: { in SimplifySetCC() 2247 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC() 2261 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC() 2369 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC() 2560 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeInstrInfo.td | 781 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), 818 (i32 GPR:$T), (i32 GPR:$F), SETULE), 848 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T),
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D | MBlazeInstrFPU.td | 200 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCISelDAGToDAG.cpp | 558 case ISD::SETULE: in getPredicateForSetCC() 592 case ISD::SETULE: in getCRIdxForSetCC()
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