| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 726 SETULT, // 1 1 0 0 True if unordered or less than enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 864 SETULT, // 1 1 0 0 True if unordered or less than enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 927 SETULT, // 1 1 0 0 True if unordered or less than enumerator
953 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 166 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; in getFCmpCondCode()
193 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 176 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
188 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
208 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 175 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
187 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
207 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 228 case ISD::SETULT: in softenSetCCOperands()
1412 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1580 case ISD::SETULT: in SimplifySetCC()
1602 case ISD::SETULT: in SimplifySetCC()
1767 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1778 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1791 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1795 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1816 if (Cond == ISD::SETULT && in SimplifySetCC()
[all …]
|
| D | LegalizeIntegerTypes.cpp | 973 case ISD::SETULT: in PromoteSetCCOperands()
1617 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1687 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
1796 ISD::SETULT); in ExpandIntRes_ADDSUB()
1801 ISD::SETULT); in ExpandIntRes_ADDSUB()
1810 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2536 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2834 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2876 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2903 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 313 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: in Select()
336 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1968 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2085 case ISD::SETULT: in SimplifySetCC()
2107 case ISD::SETULT: in SimplifySetCC()
2252 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
2255 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
2268 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
2272 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
2293 if (Cond == ISD::SETULT && in SimplifySetCC()
2384 isCondCodeLegal(ISD::SETULT, N0.getValueType())) in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 820 case ISD::SETULT: in PromoteSetCCOperands()
1441 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1540 ISD::SETULT); in ExpandIntRes_ADDSUB()
1545 ISD::SETULT); in ExpandIntRes_ADDSUB()
1554 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2235 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2511 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2548 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 78 SETULT unimplemented
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 233 case ISD::SETULT: in softenSetCCOperands()
1889 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
2004 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
2008 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2176 case ISD::SETULT: in SimplifySetCC()
2199 case ISD::SETULT: in SimplifySetCC()
2383 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
2395 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
2443 if (Cond == ISD::SETULT && in SimplifySetCC()
2508 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 1015 case ISD::SETULT: in PromoteSetCCOperands()
1692 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1762 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
1892 ISD::SETULT); in ExpandIntRes_ADDSUB()
1904 ISD::SETULT); in ExpandIntRes_ADDSUB()
1913 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2008 auto Cond = N->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT; in ExpandIntRes_UADDSUBO()
2993 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
3063 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 37 IntRegs:$fval, SETULT)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 48 defm LT_U : ComparisonInt<SETULT, "lt_u">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 47 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 233 case ISD::SETULT: in kill()
|
| D | R600ISelLowering.cpp | 132 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
138 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
819 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
820 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
857 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
858 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 488 case ISD::SETULT: in NegateCC()
701 case ISD::SETULT: in EmitInstrWithCustomInserter()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 99 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
105 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
995 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
996 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1033 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1034 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2889 case ISD::SETULT: { in get32BitZExtCompare()
3062 case ISD::SETULT: { in get32BitSExtCompare()
3218 case ISD::SETULT: { in get64BitZExtCompare()
3381 case ISD::SETULT: { in get64BitSExtCompare()
3630 case ISD::SETULT: in SelectCC()
3657 case ISD::SETULT: in SelectCC()
3703 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
3735 case ISD::SETULT: return 0; in getCRIdxForSetCC()
3756 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
3764 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
|
| D | PPCInstrQPX.td | 1013 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULT),
1060 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULT),
1119 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
1140 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
1161 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1013 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULT),
1060 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULT),
1119 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
1140 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
1161 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 549 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
562 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
575 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
588 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">;
597 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">;
|