| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 11 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
21 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
95 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
96 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
105 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
106 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]
116 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
117 ; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
[all …]
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| D | illegal-sgpr-to-vgpr-copy.ll | 4 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGP…
13 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to V…
21 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to V…
29 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to V…
37 ; ERR error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to V…
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| D | si-spill-sgpr-stack.ll | 1 …spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
11 ; SGPR: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:16
12 ; SGPR-NEXT: s_waitcnt vmcnt(0)
13 ; SGPR-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
14 ; SGPR-NEXT: s_nop 4
15 ; SGPR-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0
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| D | sgpr-control-flow.ll | 7 ; If the branch decision is made based on a value in an SGPR then all
79 ; SI: s_add_i32 [[SGPR:s[0-9]+]]
80 ; SI-NOT: s_add_i32 [[SGPR]]
103 ; FIXME: Should write to different SGPR pairs instead of copying to
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| D | add_i64.ll | 20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
32 ; SGPR as other operand.
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| D | spill-alloc-sgpr-init-bug.ll | 3 ; On Tonga and Iceland, limited SGPR availability means care must be taken to
17 ; mark 128-bit SGPR registers as used so they are unavailable for the
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| D | attr-amdgpu-num-sgpr-spill-to-smem.ll | 3 ; FIXME: SGPR-to-SMEM requires an additional SGPR always to scavenge m0
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| D | spill-offset-calculation.ll | 3 ; Test that the VGPR spiller correctly switches to SGPR offsets when the
32 ; fit in the instruction, and has to live in the SGPR offset.
85 ; in the SGPR offset.
136 ; fit in the instruction, and has to live in the SGPR offset.
189 ; in the SGPR offset.
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| D | attr-amdgpu-num-sgpr.ll | 6 ; FIXME: Vectorization can increase required SGPR count beyond limit.
7 ; FIXME: SGPR-to-SMEM requires an additional SGPR always to scavenge m0
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 11 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
21 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
99 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
100 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
109 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
110 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]
120 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
121 ; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
[all …]
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| D | sgpr-control-flow.ll | 7 ; If the branch decision is made based on a value in an SGPR then all
38 ; SI: s_add_i32 [[SGPR:s[0-9]+]]
39 ; SI-NOT: s_add_i32 [[SGPR]]
62 ; FIXME: Should write to different SGPR pairs instead of copying to
|
| D | add_i64.ll | 20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
32 ; SGPR as other operand.
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| D | spill-alloc-sgpr-init-bug.ll | 3 ; On Tonga and Iceland, limited SGPR availability means care must be taken to
17 ; mark 128-bit SGPR registers as used so they are unavailable for the
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| D | v_cndmask.ll | 22 ; This requires slightly trickier SGPR operand legalization since the
23 ; single constant bus SGPR usage is the last operand, and it should
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| D | sgpr-copy-duplicate-operand.ll | 4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 102 // SGPR registers
104 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
125 // SGPR 32-bit registers
127 (add (sequence "SGPR%u", 0, 103))> {
131 // SGPR 64-bit registers
136 // SGPR 128-bit registers
143 // SGPR 256-bit registers
154 // SGPR 512-bit registers
358 // SSrc_* Operands with an SGPR or a 32-bit immediate
370 // SCSrc_* Operands with an SGPR or a inline constant
[all …]
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| D | SIIntrinsics.td | 24 [llvm_anyint_ty, // rsrc(SGPR)
28 llvm_i32_ty, // soffset(SGPR)
42 [llvm_anyint_ty, // rsrc(SGPR)
44 llvm_i32_ty, // soffset(SGPR)
59 llvm_v8i32_ty, // rsrc(SGPR)
60 llvm_v4i32_ty, // sampler(SGPR)
75 llvm_v8i32_ty, // rsrc(SGPR)
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 193 llvm_v8i32_ty, // rsrc(SGPR)
208 llvm_v8i32_ty, // rsrc(SGPR)
223 llvm_v8i32_ty, // rsrc(SGPR)
246 llvm_v8i32_ty, // rsrc(SGPR)
254 [llvm_v4i32_ty, // rsrc(SGPR)
256 llvm_i32_ty, // offset(SGPR/VGPR/imm)
266 llvm_v4i32_ty, // rsrc(SGPR)
268 llvm_i32_ty, // offset(SGPR/VGPR/imm)
278 llvm_v4i32_ty, // rsrc(SGPR)
280 llvm_i32_ty, // offset(SGPR/VGPR/imm)
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 22 [llvm_anyint_ty, // rsrc(SGPR)
26 llvm_i32_ty, // soffset(SGPR)
40 [llvm_anyint_ty, // rsrc(SGPR)
42 llvm_i32_ty, // soffset(SGPR)
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| D | SIRegisterInfo.td | 137 // SGPR registers
139 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
165 // SGPR 32-bit registers
167 (add (sequence "SGPR%u", 0, 103))> {
168 // Give all SGPR classes higher priority than VGPR classes, because
173 // SGPR 64-bit registers
178 // SGPR 128-bit registers
185 // SGPR 256-bit registers
196 // SGPR 512-bit registers
622 // SSrc_* Operands with an SGPR or a 32-bit immediate
[all …]
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| D | AMDGPURegisterBanks.td | 10 def SGPRRegBank : RegisterBank<"SGPR",
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | inst-select-sitofp.mir | 17 ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
26 ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0
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| D | inst-select-fptoui.mir | 17 ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
26 ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 183 // Set EXEC according to a thread count packed in an SGPR input:
187 [llvm_i32_ty, // 32-bit SGPR input
633 [llvm_v8i32_ty], // rsrc(SGPR)
634 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR)
795 [llvm_v4i32_ty, // rsrc(SGPR)
797 llvm_i32_ty, // offset(SGPR/VGPR/imm)
808 llvm_v4i32_ty, // rsrc(SGPR)
810 llvm_i32_ty, // offset(SGPR/VGPR/imm)
820 [llvm_v4i32_ty, // rsrc(SGPR)
823 llvm_i32_ty, // soffset(SGPR)
[all …]
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| /external/clang/test/SemaOpenCL/ |
| D | amdgpu-num-register-attrs.cl | 23 // Check 0 SGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
|