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Searched refs:SGPR0 (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll31 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
32 ; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x…
34 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]]
71 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
72 ; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x…
74 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]]
83 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
84 ; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x…
86 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]]
148 ; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
[all …]
Dmadak.ll209 ; GCN: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}}
210 ; GCN: v_mov_b32_e32 [[SGPR0_VCOPY:v[0-9]+]], [[SGPR0]]
/external/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll31 ; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
33 ; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
36 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
71 ; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
73 ; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
76 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
85 ; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
87 ; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
90 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
152 ; GCN-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
[all …]
Dmadak.ll198 ; GCN: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xa|0x28}}
199 ; GCN: v_mov_b32_e32 [[SGPR0_VCOPY:v[0-9]+]], [[SGPR0]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-amdgcn.cvt.pkrtz.mir17 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
26 ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
30 ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
Dinst-select-minnum.mir16 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
32 ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
36 ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
Dinst-select-maxnum.mir16 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
32 ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
36 ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
Dinst-select-or.mir16 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
27 ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[SGPR0]], [[SGPR1]]
Dinst-select-ashr.mir17 ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
31 ; GCN: [[SS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SGPR0]], [[SGPR1]]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td21 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
29 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14,
59 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14,
71 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
DSIMachineFunctionInfo.h115 return AMDGPU::SGPR0 + NumUserSGPRs; in getNextUserSGPR()
119 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; in getNextSystemSGPR()
DSIRegisterInfo.cpp106 classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets); in SIRegisterInfo()
DSIISelLowering.cpp48 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) { in findFirstFreeSGPR()
49 return AMDGPU::SGPR0 + Reg; in findFirstFreeSGPR()
DSIInstructions.td368 SCC = S_CMPK_EQ_I32 SGPR0, imm
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp332 return AMDGPU::SGPR0 + NumUserSGPRs; in getNextUserSGPR()
336 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; in getNextSystemSGPR()
DAMDGPUCallingConv.td23 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
59 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
DSIInsertWaitcnts.cpp93 unsigned SGPR0; member
497 assert(Reg >= RegisterEncoding.SGPR0 && Reg < SQ_MAX_PGM_SGPRS); in getRegInterval()
498 Result.first = Reg - RegisterEncoding.SGPR0 + NUM_ALL_VGPRS; in getRegInterval()
1866 RegisterEncoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0); in runOnMachineFunction()
1868 RegisterEncoding.SGPR0 + HardwareLimits.NumSGPRsMax - 1; in runOnMachineFunction()
DSIRegisterInfo.cpp76 classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets); in SIRegisterInfo()
1174 REG_RANGE(AMDGPU::SGPR0, AMDGPU::SGPR103, SGPR32RegNames); in getRegAsmName()
DSIFrameLowering.cpp394 auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in in emitEntryFunctionScratchSetup()
DSOPInstructions.td618 // SCC = S_CMPK_EQ_I32 SGPR0, imm
DSIISelLowering.cpp107 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) { in findFirstFreeSGPR()
108 return AMDGPU::SGPR0 + Reg; in findFirstFreeSGPR()
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUUsage.rst2119 for enabled registers are dense starting at SGPR0: the first enabled register is
2120 SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
3849 ``debugtrap(arg)`` ``s_trap 0x01`` ``SGPR0-1``: Reserved for HSA
3853 ``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: Causes dispatch to be