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Searched refs:SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-uniphier/clk/
Dpll-ld4.c30 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { in upll_init()
97 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { in vpll_init()
/external/u-boot/arch/arm/mach-uniphier/
Dsg-regs.h88 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) macro