Searched refs:SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT (Results 1 – 5 of 5) sorted by relevance
322 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in brw_instruction_name()982 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in has_side_effects()
432 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, enumerator
597 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()601 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()2011 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in generate_code()
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in is_send_from_grf()810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in size_read()1398 prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) { in emit_gs_thread_end()5165 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in get_lowered_simd_width()
1877 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT; in emit_gs_control_data_bits()2750 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT : in nir_emit_tcs_intrinsic()2774 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT : in nir_emit_tcs_intrinsic()