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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dp8-scalar_vector_conversions.ll543 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
544 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
554 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
555 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
571 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
572 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
582 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
583 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
823 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4
824 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dbfe-patterns.ll27 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
28 ; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
30 ; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
31 ; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
34 ; GCN: [[SHL]]
67 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
68 ; GCN: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]]
103 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
104 ; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
106 ; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
[all …]
Dshift-i64-opts.ll126 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]
127 ; GCN: buffer_store_dword [[SHL]]
138 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
139 ; GCN: buffer_store_short [[SHL]]
150 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
151 ; GCN: buffer_store_short [[SHL]]
162 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]
163 ; GCN: buffer_store_byte [[SHL]]
174 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
175 ; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 2, [[SHL]]
[all …]
Dshl-add-to-add-shl.ll7 ; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
8 ; CHECK: v_add_u32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]]
24 ; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
25 ; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiAluCode.h36 SHL = 0x17, enumerator
93 case SHL: in lanaiAluCodeToString()
113 .Case("sh", SHL) in stringToLanaiAluCode()
135 case ISD::SHL: in isdToLanaiAluCode()
136 return AluCode::SHL; in isdToLanaiAluCode()
/external/llvm/lib/Target/Lanai/
DLanaiAluCode.h36 SHL = 0x17, enumerator
93 case SHL: in lanaiAluCodeToString()
113 .Case("sh", SHL) in stringToLanaiAluCode()
135 case ISD::SHL: in isdToLanaiAluCode()
136 return AluCode::SHL; in isdToLanaiAluCode()
/external/llvm/test/CodeGen/AMDGPU/
Dshift-i64-opts.ll126 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]
127 ; GCN: buffer_store_dword [[SHL]]
138 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
139 ; GCN: buffer_store_short [[SHL]]
150 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
151 ; GCN: buffer_store_short [[SHL]]
162 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]
163 ; GCN: buffer_store_byte [[SHL]]
174 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
175 ; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 2, [[SHL]]
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_sbr_imdct_using_fft.s343 SHL V12.4S, V12.4S, #1
346 SHL V22.4S, V22.4S, #1
348 SHL V9.4S, V9.4S, #1
351 SHL V2.4S, V2.4S, #1
353 SHL V24.4S, V24.4S, #1
356 SHL V7.4S, V7.4S, #1
358 SHL V13.4S, V13.4S, #1
361 SHL V23.4S, V23.4S, #1
363 SHL V10.4S, V10.4S, #1
366 SHL V3.4S, V3.4S, #1
[all …]
Dixheaacd_imdct_using_fft.s393 SHL v12.4S, v12.4S, #3
396 SHL v22.4S, v22.4S, #3
398 SHL v9.4S, v9.4S, #3
401 SHL v2.4S, v2.4S, #3
403 SHL v24.4S, v24.4S, #3
406 SHL v7.4S, v7.4S, #3
408 SHL v13.4S, v13.4S, #3
411 SHL v23.4S, v23.4S, #3
413 SHL v10.4S, v10.4S, #3
416 SHL v3.4S, v3.4S, #3
[all …]
Dixheaacd_inv_dit_fft_8pt.s109 SHL v7.4s, v7.4s, #1
110 SHL v10.4s, v10.4s, #1
131 SHL v9.4s, v9.4s, #1
132 SHL v13.4s, v13.4s, #1
/external/llvm/test/CodeGen/PowerPC/
Dp8-scalar_vector_conversions.ll687 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
688 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
698 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
699 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
721 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
722 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
732 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
733 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
1039 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4
1040 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
[all …]
Dload-v4i8-improved.ll20 ; CHECK-BE: sldi [[SHL:[0-9]+]], [[GPR]], 32
21 ; CHECK-BE: mtvsrd [[VSR:[0-9]+]], [[SHL]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-shl.mir15 ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[COPY1]]
31 ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY]], [[COPY1]]
48 ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY]], [[COPY2]]
64 ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY]], [[COPY1]]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
138 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
151 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
157 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
178 { ISD::SHL, MVT::v16i8, 1 }, in getArithmeticInstrCost()
181 { ISD::SHL, MVT::v8i16, 1 }, in getArithmeticInstrCost()
184 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
[all …]
/external/lzma/Asm/x86/
DLzmaDecOpt.asm61 PMULT equ (1 SHL PSHIFT)
62 PMULT_HALF equ (1 SHL (PSHIFT - 1))
63 PMULT_2 equ (1 SHL (PSHIFT + 1))
145 kBitModelTotal equ (1 SHL kNumBitModelTotalBits)
147 kBitModelOffset equ ((1 SHL kNumMoveBits) - 1)
148 kTopValue equ (1 SHL 24)
452 kNumPosStatesMax equ (1 SHL kNumPosBitsMax)
455 kLenNumLowSymbols equ (1 SHL kLenNumLowBits)
457 kLenNumHighSymbols equ (1 SHL kLenNumHighBits)
471 kNumFullDistances equ (1 SHL (kEndPosModelIndex SHR 1))
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
98 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]]
99 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
128 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]]
129 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
Dshift-128-kb.ll14 ; CHECK-NEXT: [[SHL:%.*]] = shl i128 [[CONV2]], [[SH_PROM]]
15 ; CHECK-NEXT: [[SHR:%.*]] = ashr i128 [[SHL]], [[SH_PROM]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-itofp.mir142 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
143 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
177 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
178 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
212 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
213 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
Dlegalize-gep.mir29 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]]
30 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
326 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
350 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
354 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. in getArithmeticInstrCost()
389 if ((ISD != ISD::SHL && ISD != ISD::SRL && ISD != ISD::SRA) || in getArithmeticInstrCost()
398 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
413 { ISD::SHL, MVT::v8i16, 1 }, // psllw. in getArithmeticInstrCost()
414 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
415 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
445 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-legalize-sitofp.mir93 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
94 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
125 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
126 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
209 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
210 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
241 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
242 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
98 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]]
99 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
128 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]]
129 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Drotate.ll137 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[LSHAMTCONV]]
138 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
164 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[LSHAMTCONV]]
165 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
193 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[LSHAMT]]
194 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
216 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[LSHAMT]]
217 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
Dpr17827.ll37 ; CHECK-NEXT: [[SHL:%.*]] = and i8 [[ANDP]], -64
38 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
53 ; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
54 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUNodes.td86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
87 def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>;
105 // SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128

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