| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 435 SIGN_EXTEND_VECTOR_INREG, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 480 SIGN_EXTEND_VECTOR_INREG, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 329 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
683 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 246 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 622 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
2130 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
2441 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2458 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
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| D | LegalizeIntegerTypes.cpp | 106 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3357 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1399 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); in visit()
5787 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in tryToFoldExtendOfConstant()
5824 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
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| D | SelectionDAG.cpp | 1059 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 68 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
289 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
679 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
1650 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2338 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
2658 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2675 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
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| D | LegalizeVectorOps.cpp | 388 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
713 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 289 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 108 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3513 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1554 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); in visit()
7913 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in tryToFoldExtendOfConstant()
7950 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
9248 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
9252 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)) in visitSIGN_EXTEND_INREG()
16754 Opcode != ISD::SIGN_EXTEND_VECTOR_INREG && in combineTruncationShuffle()
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| D | SelectionDAG.cpp | 1140 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
3264 case ISD::SIGN_EXTEND_VECTOR_INREG: { in ComputeNumSignBits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 85 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
140 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 644 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 899 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 896 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
897 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
898 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
952 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1111 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom); in X86TargetLowering()
1112 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom); in X86TargetLowering()
1113 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom); in X86TargetLowering()
1318 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i64, Custom); in X86TargetLowering()
1319 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i32, Custom); in X86TargetLowering()
1322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4577 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
4778 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 387 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 347 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4874 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
5173 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 852 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
853 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
854 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
1057 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom); in X86TargetLowering()
1058 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom); in X86TargetLowering()
1059 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom); in X86TargetLowering()
16486 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) && in LowerExtendedLoad()
21697 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
27571 : ISD::SIGN_EXTEND_VECTOR_INREG, in reduceVMULWidth()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 1656 // FastEmit functions for ISD::SIGN_EXTEND_VECTOR_INREG.
5517 …case ISD::SIGN_EXTEND_VECTOR_INREG: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0,…
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