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Searched refs:SIM0_RBASE (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dscg.c716 reg = readl(SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
721 writel(reg, SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
784 reg = readl(SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
786 writel(reg, SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
Dsoc.c114 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); in reset_cpu()
/external/u-boot/arch/arm/include/asm/arch-mx7ulp/
Dimx-regs.h145 #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) macro