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Searched refs:SI_SH_REG_OFFSET (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h86 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
90 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
Dradv_cmd_buffer.c3226 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
3227 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
3234 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
3235 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
3236 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) | in radv_cs_emit_indirect_draw_packet()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h155 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
158 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c58 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) { in si_pm4_set_reg()
60 reg -= SI_SH_REG_OFFSET; in si_pm4_set_reg()
Dsi_state_draw.c763 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
764 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
784 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
785 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
786 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) | in si_emit_draw_packets()
Dsi_descriptors.c2000 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2); in si_emit_shader_pointer_head()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h172 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
175 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
Dr600d_common.h31 #define SI_SH_REG_OFFSET 0x0000B000 macro
/external/mesa3d/src/amd/common/
Dac_debug.c258 ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib); in ac_parse_packet3()
Dsid.h30 #define SI_SH_REG_OFFSET 0x0000B000 macro