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Searched refs:SMIN (Results 1 – 25 of 56) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2107 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
2120 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" in getMinMaxReductionCost()
2122 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" in getMinMaxReductionCost()
2124 {ISD::SMIN, MVT::v8i16, 2}, in getMinMaxReductionCost()
2132 {ISD::SMIN, MVT::v2i64, 3}, in getMinMaxReductionCost()
2134 {ISD::SMIN, MVT::v4i32, 1}, in getMinMaxReductionCost()
2136 {ISD::SMIN, MVT::v8i16, 1}, in getMinMaxReductionCost()
2138 {ISD::SMIN, MVT::v8i32, 3}, in getMinMaxReductionCost()
2143 {ISD::SMIN, MVT::v4i64, 2}, in getMinMaxReductionCost()
2145 {ISD::SMIN, MVT::v8i32, 1}, in getMinMaxReductionCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvec_minmax_match.ll34 ; (X >s Y) ? 0 : Z ==> (Z >s 0) ? 0 : Z ==> SMIN(Z, 0)
49 ; (X <s Y) ? Z : 0 ==> (Z <s 0) ? Z : 0 ==> SMIN(Z, 0)
162 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
177 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dminmax-fold.ll225 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
294 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
366 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
383 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
400 ; (X >s C1) ? SMIN(X, C2) : C1 ==> SMAX(SMIN(X, C2), C1)
417 ; (X <s C1) ? SMAX(X, C2) : C1 ==> SMIN(SMAX(X, C1), C2)
Dselect_meta.ll168 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
Dselect.ll613 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h972 X86_INTRINSIC_DATA(avx512_mask_pmins_b_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
973 X86_INTRINSIC_DATA(avx512_mask_pmins_b_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
974 X86_INTRINSIC_DATA(avx512_mask_pmins_b_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
975 X86_INTRINSIC_DATA(avx512_mask_pmins_d_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
976 X86_INTRINSIC_DATA(avx512_mask_pmins_d_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
977 X86_INTRINSIC_DATA(avx512_mask_pmins_d_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
978 X86_INTRINSIC_DATA(avx512_mask_pmins_q_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
979 X86_INTRINSIC_DATA(avx512_mask_pmins_q_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
980 X86_INTRINSIC_DATA(avx512_mask_pmins_q_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
981 X86_INTRINSIC_DATA(avx512_mask_pmins_w_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h325 SMIN, SMAX, UMIN, UMAX, enumerator
DSelectionDAG.h1168 case ISD::SMIN:
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h360 SMIN, SMAX, UMIN, UMAX, enumerator
/external/llvm/test/Transforms/InstCombine/
Dselect.ll608 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
1273 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
1321 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dselect.ll484 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp207 case ISD::SMIN: return "smin"; in getOperationName()
DLegalizeVectorOps.cpp331 case ISD::SMIN: in LegalizeOp()
DLegalizeIntegerTypes.cpp78 case ISD::SMIN: in PromoteIntegerResult()
1382 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
1684 case ISD::SMIN: in getExpandedMinMaxOps()
DLegalizeVectorTypes.cpp114 case ISD::SMIN: in ScalarizeVectorResult()
692 case ISD::SMIN: in SplitVectorResult()
2095 case ISD::SMIN: in WidenVectorResult()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp247 case ISD::SMIN: return "smin"; in getOperationName()
DLegalizeVectorTypes.cpp118 case ISD::SMIN: in ScalarizeVectorResult()
749 case ISD::SMIN: in SplitVectorResult()
1745 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; in SplitVecOp_VECREDUCE()
2303 case ISD::SMIN: in WidenVectorResult()
DSelectionDAG.cpp3004 case ISD::SMIN: in computeKnownBits()
3011 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
3318 case ISD::SMIN: in ComputeNumSignBits()
3325 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
4150 case ISD::SMIN: return std::make_pair(C1.sle(C2) ? C1 : C2, true); in FoldValue()
4476 case ISD::SMIN: in getNode()
DLegalizeVectorOps.cpp390 case ISD::SMIN: in LegalizeOp()
DLegalizeIntegerTypes.cpp80 case ISD::SMIN: in PromoteIntegerResult()
1454 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
1759 case ISD::SMIN: in getExpandedMinMaxOps()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp225 setTargetDAGCombine(ISD::SMIN); in SITargetLowering()
2701 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
2805 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
2871 case ISD::SMIN: in PerformDAGCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp99 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp402 setOperationAction(ISD::SMIN, MVT::i16, Legal); in SITargetLowering()
561 setOperationAction(ISD::SMIN, MVT::v2i16, Legal); in SITargetLowering()
583 setOperationAction(ISD::SMIN, MVT::v4i16, Custom); in SITargetLowering()
627 setTargetDAGCombine(ISD::SMIN); in SITargetLowering()
3638 case ISD::SMIN: in LowerOperation()
6953 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
7099 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
7224 case ISD::SMIN: in performExtractVectorEltCombine()
7813 case ISD::SMIN: in PerformDAGCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp340 setOperationAction(ISD::SMIN, Ty, Legal); in addMSAIntType()
1994 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2006 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp605 setOperationAction(ISD::SMIN, VT, Expand); in initActions()

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