| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 SMULO, UMULO, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 257 SMULO, UMULO, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 337 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; in mightUseCTR()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 232 case ISD::SMULO: return "smulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 136 case ISD::SMULO: in PromoteIntegerResult()
772 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
1402 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 3376 case ISD::SMULO: { in ExpandNode()
3386 bool isSigned = Node->getOpcode() == ISD::SMULO; in ExpandNode()
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| D | SelectionDAG.cpp | 2128 case ISD::SMULO: in computeKnownBits()
2619 case ISD::SMULO: in ComputeNumSignBits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 274 case ISD::SMULO: return "smulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 138 case ISD::SMULO: in PromoteIntegerResult()
808 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
1477 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 3526 case ISD::SMULO: { in ExpandNode()
3536 bool isSigned = Node->getOpcode() == ISD::SMULO; in ExpandNode()
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| D | SelectionDAG.cpp | 2540 case ISD::SMULO: in computeKnownBits()
3356 case ISD::SMULO: in ComputeNumSignBits()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1708 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
2961 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2963 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3082 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1720 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
2995 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2997 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
3116 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 118 case ISD::SMULO: in PromoteIntegerResult()
647 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO()
1157 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 860 case ISD::SMULO: in LegalizeOp()
3599 case ISD::SMULO: { in ExpandNode()
3609 bool isSigned = Node->getOpcode() == ISD::SMULO; in ExpandNode()
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| D | SelectionDAG.cpp | 1737 case ISD::SMULO: in ComputeMaskedBits()
2172 case ISD::SMULO: in ComputeNumSignBits()
6022 case ISD::SMULO: return "smulo"; in getOperationName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | xmulo.ll | 90 ; SMULO
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 247 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
248 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
1644 case ISD::SMULO: in getAArch64XALUOOp()
1647 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()
2346 case ISD::SMULO: in LowerOperation()
3639 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
4088 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 616 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
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| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 294 ; SMULO
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 883 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 317 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering()
318 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering()
1938 case ISD::SMULO: in getAArch64XALUOOp()
1941 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp()
2036 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes()
2816 case ISD::SMULO: in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1122 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()
1127 setOperationAction(ISD::SMULO, MVT::i8, Expand); in X86TargetLowering()
10087 case ISD::SMULO: in LowerXALUO()
10445 case ISD::SMULO: in LowerOperation()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1588 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering()
15905 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
15918 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
16549 Cond.getOperand(0).getOpcode() == ISD::SMULO || in LowerBRCOND()
16602 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
16628 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
20516 case ISD::SMULO: in LowerXALUO()
21748 case ISD::SMULO: in LowerOperation()
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