Searched refs:SOPC (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 71 SOPC Instructions
73 All SOPC instructions are supported.
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 27 field bits<1> SOPC = 0;
63 let TSFlags{7} = SOPC;
305 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
312 let SOPC = 1;
|
| D | SIDefines.h | 24 SOPC = 1 << 7, enumerator
|
| D | SIInstrInfo.h | 224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
|
| D | SIInstructions.td | 326 // SOPC Instructions
|
| D | SIInstrInfo.td | 871 string opName, list<dag> pattern = []> : SOPC <
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 34 field bit SOPC = 0;
130 let TSFlags{4} = SOPC;
|
| D | SIDefines.h | 28 SOPC = 1 << 4, enumerator
|
| D | SOPInstructions.td | 696 // SOPC Instructions
709 class SOPC <bits<7> op, dag outs, dag ins, string asm,
716 let SOPC = 1;
725 string opName, list<dag> pattern = []> : SOPC <
784 def S_SET_GPR_IDX_ON : SOPC <0x11,
|
| D | SIInstrInfo.h | 341 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
345 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUUsage.rst | 4217 SOPC subsubsection
4227 For full list of supported instructions, refer to "SOPC Instructions" in ISA Manual.
|
| D | AMDGPUAsmGFX7.rst | 468 SOPC chapter
|
| D | AMDGPUAsmGFX8.rst | 487 SOPC chapter
|
| D | AMDGPUAsmGFX9.rst | 639 SOPC chapter
|