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Searched refs:SPI (Results 1 – 25 of 193) sorted by relevance

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/external/u-boot/drivers/spi/
DKconfig1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
22 bool "Altera SPI driver"
24 Enable the Altera SPI driver. This driver can be used to
25 access the SPI NOR flash on platforms embedding this Altera
30 bool "Andestech ATCSPI200 SPI driver"
[all …]
/external/u-boot/drivers/mtd/spi/
DKconfig1 menu "SPI Flash Support"
4 bool "Enable Driver Model for SPI flash"
7 Enable driver model for SPI flash. This SPI flash interface
9 implemented by the SPI flash uclass. There is one standard
10 SPI flash driver which knows how to probe most chips
14 during the transition parent. SPI and SPI flash must be
19 bool "Support sandbox SPI flash device"
23 provided instead. Drivers can be connected up to the sandbox SPI
24 bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
25 device. Typically the contents of the emulated SPI flash device is
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/external/u-boot/doc/device-tree-bindings/spi/
Dspi-bus.txt1 SPI (Serial Peripheral Interface) busses
3 SPI busses can be described with a node for the SPI master device
4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
6 SPI master mode. This binding does not describe SPI controllers
9 The SPI master node requires the following properties:
11 address on the SPI bus.
13 - compatible - name of SPI bus controller following generic names
16 No other properties are required in the SPI bus node. It is assumed
17 that a driver for an SPI bus device will understand that it is an SPI bus.
[all …]
Dsoft-spi.txt1 Soft SPI
3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
4 SPI bus. No SPI host is required for this to work. The down-side is that the
5 performance will typically be much lower than a real SPI bus.
7 The soft SPI node requires the following properties:
11 cs-gpios: GPIOs to use for SPI chip select (output)
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
Dspi-atcspi200.txt1 Andestech ATCSPI200 SPI controller Device Tree Bindings
3 ATCSPI200 is a Serial Peripheral Interface (SPI) controller
4 which serves as a SPI master or a SPI slave.
11 - #address-cells: <1>, as required by generic SPI binding.
12 - #size-cells: <0>, also as required by generic SPI binding.
15 - spi-max-frequency: Maximum SPI clocking speed of device in Hz.
Dspi-ath79.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
6 - #address-cells: <1>, as required by generic SPI binding.
7 - #size-cells: <0>, also as required by generic SPI binding.
9 Child nodes as per the generic SPI binding.
/external/u-boot/doc/SPI/
DREADME.sandbox-spi1 Sandbox SPI/SPI Flash Implementation
4 U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled
15 SPI bus number (typically 0)
16 SPI chip select number (typically 0)
17 SPI chip to emulate
37 SPI flash test:
52 Since the SPI bus is fully implemented as well as the SPI flash connected to
53 it, you can also use low-level SPI commands to access the flash. For example
63 Note that the sandbox SPI implementation was written by Mike Frysinger
Dstatus.txt1 Status on SPI subsystem:
4 SPI COMMAND (common/cmd_sf, cmd_spi):
7 SPI FLASH (drivers/mtd/spi):
8 - sf_probe.c: SPI flash probing code.
9 - sf_ops.c: SPI flash operations code.
10 - sf.c: SPI flash interface, which interacts controller driver.
20 SPI DRIVERS (drivers/spi):
DREADME.dual-flash1 SPI/QSPI Dual flash connection modes:
4 This describes how SPI/QSPI flash memories are connected to a given
22 | SPI/QSPI |<======================>| (SPI/QSPI) |
36 | | | CLK | (SPI/QSPI) |
39 | SPI/QSPI |------------|----|---->| |
42 | | CLK | | (SPI/QSPI) |
66 | | CLK | (SPI/QSPI) |
69 | SPI/QSPI |---------------------->| |
72 | | CLK | (SPI/QSPI) |
DREADME.ti_qspi_flash11 from Quad SPI flash devices.
23 SPI mode
25 SPI mode uses mtd spi framework for transfer and reception of data.
33 In this, SPI controller is configured using configuration port and then
/external/freetype/src/tools/
Dtest_trig.c9 #define SPI (PI/FT_ANGLE_PI) macro
30 d2 = cos( i*SPI ); in test_cos()
56 d2 = sin( i*SPI ); in test_sin()
82 d2 = tan( i*SPI ); in test_tan()
109 a = i*SPI; in test_atan2()
144 a = ( i*SPI ); in test_unit()
176 v.x = (FT_Fixed)( l * cos( i*SPI ) ); in test_length()
177 v.y = (FT_Fixed)( l * sin( i*SPI ) ); in test_length()
202 ra = rotate*SPI; in test_rotate()
214 a = i*SPI; in test_rotate()
/external/u-boot/doc/
DREADME.sh7753evb12 - SPI ROM 8MB
35 You can write MAC address to SPI ROM.
57 Update SPI ROM:
61 2. Probe SPI device.
64 3. Erase SPI ROM.
66 4. Write u-boot image to SPI ROM.
DREADME.sh7752evb12 - SPI ROM 8MB
35 You can write MAC address to SPI ROM.
57 Update SPI ROM:
61 2. Probe SPI device.
64 3. Erase SPI ROM.
66 4. Write u-boot image to SPI ROM.
DREADME.at9121 - Dataflash on SPI chip select 1 (default)
22 - Dataflash on SPI chip select 0 (dataflash card)
43 - Dataflash on SPI chip select 0 (default)
44 - Dataflash on SPI chip select 3 (dataflash card)
64 - Dataflash on SPI chip select 0 (dataflash card)
104 - Dataflash on SPI chip select 0
123 - Serialflash/Dataflash on SPI chip select 0
144 - Serialflash on SPI chip select 0
/external/ltp/testcases/network/stress/ipsec/
Dipsec_lib.sh41 S) SPI=$2;;
79 SPI=${SPI:-1000}
189 local spi_1="0x$SPI"
190 local spi_2="0x$(( $SPI + 1 ))"
201 local spi_1="0x$(( $SPI + 1 ))"
202 local spi_2="0x$SPI"
256 local spi_1="spi 0x$SPI"
257 local spi_2="spi 0x$(( $SPI + 1 ))"
267 local spi_1="spi 0x$(( $SPI + 1 ))"
268 local spi_2="spi 0x$SPI"
/external/u-boot/board/renesas/sh7757lcr/
DREADME.sh7757lcr12 - SPI ROM 8MB
43 You can write MAC address to SPI ROM.
67 Update SPI ROM:
71 2. Probe SPI device.
74 3. Erase SPI ROM.
76 4. Write u-boot image to SPI ROM.
/external/u-boot/board/phytec/pcm058/
DREADME23 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
28 DIP-1 set to off: Boot first from NAND, then try SPI
29 DIP-1 set to on: Boot first from SD, then try SPI
33 RBL loads from SPI-NOR. The SPL tries then to load from the same
34 device where SPL was loaded (SD or SPI). Booting from NAND is
/external/u-boot/board/davinci/da8xxevm/
DKconfig18 bool "MAC address in SPI Flash"
22 their MAC address in SPI Flash from the factory
23 Enable this option to read the MAC from SPI Flash
29 their MAC address in SPI Flash from the factory,
/external/u-boot/board/freescale/mx28evk/
DREADME26 To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
48 "make mx28evk_spi_config" - store environment variables into SPI NOR flash
56 mx28evk does not come with SPI NOR flash populated from the factory either.
58 To get SPI communication to work R320, R321,R322 and C178 need to be populated.
62 to generate a binary to be flashed into SPI NOR.
/external/u-boot/doc/driver-model/
Dspi-howto.txt1 How to port a SPI driver to driver model
5 exynos SPI driver to driver model (DM) and the example code is based
11 Before driver model, SPI drivers have their own private structure which
13 exists, but now it is 'per-child data' for the SPI bus. Each child of the
14 SPI bus is a SPI slave. The information that was stored in the
16 SPI bus.
26 SPI's buses private data.
39 1. Enable driver mode for SPI and SPI flash
163 empty SPI driver. You still have empty methods in your driver, but we will
285 struct spi_bus *bus; /* Pointer to our SPI bus info */
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/external/u-boot/board/boundary/nitrogen6x/
DREADME.mx6qsabrelite11 boards boot from the SPI NOR flash. These boards need to be reflashed with
13 will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
22 To update the SPI-NOR on the SabreLite board without the Freescale
38 (the default one the board is shipped with, starting from the SPI NOR) and
50 the Freescale manufacturing tool in order to reflash the SPI-NOR.
/external/u-boot/board/Arcturus/ucp1020/
DREADME3 DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
15 SPI Flash or NOR flash
21 SPI boot image:
25 SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
/external/u-boot/doc/device-tree-bindings/exynos/
Disp-spi.txt1 Exynos ISP SPI Subsystem
3 The device node for ISP SPI subsytem.
5 ISP SPI have no individual interrupts hence we add ad dummy interrupt node
/external/u-boot/board/phytec/pfla02/
DREADME19 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
23 SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI
24 SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI
/external/u-boot/board/freescale/p1010rdb/
DREADME.P1010RDB-PB18 - 16M bytes SPI memory
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
85 => run boot_spi (boot from SPI flash)
102 Since pins multiplexing, TDM and CAN are muxed with SPI flash.
103 SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
113 To enable SDHC in case of NOR/NAND/SPI boot
140 3. For SPI boot
164 3. SPI boot

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