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Searched refs:SPLL_CON1_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dexynos5_setup.h473 #define SPLL_CON1_VAL NOT_AVAILABLE macro
740 #define SPLL_CON1_VAL 0x0020f300 macro
Dclock_init_exynos5.c897 writel(SPLL_CON1_VAL, &clk->spll_con1); in exynos5420_system_clock_init()