| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | special-reg-acore.ll | 42 ; ACORE: msr SPSR_fsxc, r0
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| /external/llvm/test/CodeGen/ARM/ |
| D | special-reg-acore.ll | 42 ; ACORE: msr SPSR_fsxc, r0
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 280 case SPSR_fsxc: in GetName()
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| D | instructions-aarch32.h | 872 SPSR_fsxc = 0x1f enumerator
880 VIXL_ASSERT(reg <= SPSR_fsxc); in MaskedSpecialRegister()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1437 msr SPSR_fsxc, #5
1442 msr SPSR_fsxc, #40, #2
1443 msr SPSR_fsxc, $40, $2
1444 msr SPSR_fsxc, 40, 2
1445 msr SPSR_fsxc, (2 * 20), (1 << 1)
1461 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
1466 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1467 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1468 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1469 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
[all …]
|
| D | basic-thumb2-instructions.s | 1571 msr SPSR_fsxc, r5
1587 @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1439 msr SPSR_fsxc, #5
1444 msr SPSR_fsxc, #40, #2
1445 msr SPSR_fsxc, $40, $2
1446 msr SPSR_fsxc, 40, 2
1447 msr SPSR_fsxc, (2 * 20), (1 << 1)
1463 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
1468 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1469 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1470 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1471 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
[all …]
|
| D | basic-thumb2-instructions.s | 1619 msr SPSR_fsxc, r5
1635 @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 400 0x05,0xf0,0x6f,0xe3 = msr SPSR_fsxc, #5
414 0x00,0xf0,0x6f,0xe1 = msr SPSR_fsxc, r0
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| D | basic-thumb2-instructions.s.cs | 503 0x95,0xf3,0x00,0x8f = msr SPSR_fsxc, r5
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 923 msr SPSR_fsxc, #5
938 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
953 msr SPSR_fsxc, r0
968 @ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
|
| D | basic-thumb2-instructions.s | 1188 msr SPSR_fsxc, r5
1203 @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 860 # CHECK: msr SPSR_fsxc, #5
863 # CHECK: msr SPSR_fsxc, #40, #2
894 # CHECK: msr SPSR_fsxc, r0
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| D | thumb2.txt | 1130 # CHECK: msr SPSR_fsxc, r5
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 860 # CHECK: msr SPSR_fsxc, #5
863 # CHECK: msr SPSR_fsxc, #40, #2
894 # CHECK: msr SPSR_fsxc, r0
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| D | thumb2.txt | 1130 # CHECK: msr SPSR_fsxc, r5
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 759 # CHECK: msr SPSR_fsxc, #5
789 # CHECK: msr SPSR_fsxc, r0
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| D | thumb2.txt | 1013 # CHECK: msr SPSR_fsxc, r5
|