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Searched refs:SR0 (Results 1 – 2 of 2) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/
Dif-pred-non-void.ll58 ; CHECK: %[[SR0:[a-zA-Z0-9]+]] = srem i32 %[[SRA0]], %[[SRA1]]
59 ; CHECK: %[[SR1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SR0]], i32 0
/external/u-boot/arch/powerpc/include/asm/
Dprocessor.h1158 #define SR0 0 macro