| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
97 case SRA: in lanaiAluCodeToString()
115 .Case("sha", SRA) in stringToLanaiAluCode()
139 case ISD::SRA: in isdToLanaiAluCode()
140 return AluCode::SRA; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
97 case SRA: in lanaiAluCodeToString()
115 .Case("sha", SRA) in stringToLanaiAluCode()
139 case ISD::SRA: in isdToLanaiAluCode()
140 return AluCode::SRA; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
140 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
153 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
180 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
183 { ISD::SRA, MVT::v8i16, 2 }, in getArithmeticInstrCost()
186 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost()
189 { ISD::SRA, MVT::v2i64, 2 }, in getArithmeticInstrCost()
193 { ISD::SRA, MVT::v32i8, 4 }, in getArithmeticInstrCost()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
308 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
309 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
310 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
328 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
330 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
352 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
356 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
389 if ((ISD != ISD::SHL && ISD != ISD::SRL && ISD != ISD::SRA) || in getArithmeticInstrCost()
400 { ISD::SRA, MVT::v16i16, 1 }, // psraw. in getArithmeticInstrCost()
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
|
| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
|
| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
111 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); in emit_single_op()
133 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 73 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
552 return DAG.getNode(ISD::SRA, N->getDebugLoc(), in PromoteIntRes_SRA()
785 case ISD::SRA: in PromoteIntegerOperand()
1149 case ISD::SRA: in ExpandIntegerResult()
1318 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1320 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1323 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1325 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1329 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1337 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 132 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
135 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
138 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
141 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|
| /external/llvm/test/CodeGen/X86/ |
| D | pr14204.ll | 4 ; SLL/SRA.
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 88 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
667 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
956 case ISD::SRA: in PromoteIntegerOperand()
1469 case ISD::SRA: in ExpandIntegerResult()
1559 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1561 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1564 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1566 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1570 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1578 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GlobalOpt/ |
| D | globalsra-multigep.ll | 7 ; We cannot SRA here due to the second gep meaning the access to g_data may be to either element
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 171 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
174 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
177 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
180 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
919 case ISD::SRA: in PromoteIntegerOperand()
1394 case ISD::SRA: in ExpandIntegerResult()
1484 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1486 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1489 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1491 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1495 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1503 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
[all …]
|
| D | LegalizeVectorOps.cpp | 280 case ISD::SRA: in LegalizeOp()
615 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
771 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
828 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 98 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
101 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
607 case ISD::SRA: in LowerShifts()
608 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
827 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
987 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNodes.td | 86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
89 def SPUvec_sra: SDNode<"ISD::SRA", SPUvecshift_type, []>;
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 91 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
94 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
728 case ISD::SRA: in LowerShifts()
729 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
948 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1130 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 236 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
239 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
242 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
245 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 234 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
237 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
240 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
243 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|