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Searched refs:SRDS_PLLCR0_FRATE_SEL_5 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dimmap_ls102xa.h331 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch2.h561 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h2554 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
2635 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro