| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 78 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
79 SRI.isValid(); in init()
80 ++SRI) in init()
81 if (!MCSubRegIterator(*SRI, &RI).isValid()) in init()
83 Uses.insert(*SRI); in init()
127 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
128 SRI.isValid(); in init()
129 ++SRI) { in init()
130 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
134 if (R == *SRI) { in init()
[all …]
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
33 if (*SRI == Idx) in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
45 return *SRI; in getSubRegIndex()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | GCNSchedStrategy.cpp | 34 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in initialize() local
52 SGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
53 SRI->getSGPRPressureSet()); in initialize()
54 VGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
55 SRI->getVGPRPressureSet()); in initialize()
64 const SIRegisterInfo *SRI, in initCandidate() argument
86 unsigned NewSGPRPressure = Pressure[SRI->getSGPRPressureSet()]; in initCandidate()
87 unsigned NewVGPRPressure = Pressure[SRI->getVGPRPressureSet()]; in initCandidate()
112 Cand.RPDelta.Excess = PressureChange(SRI->getVGPRPressureSet()); in initCandidate()
117 Cand.RPDelta.Excess = PressureChange(SRI->getSGPRPressureSet()); in initCandidate()
[all …]
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| D | AMDGPUMachineCFGStructurizer.cpp | 2105 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2106 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2116 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2117 PHILinearize::PHISourceT Source = *SRI; in prunePHIInfo()
2149 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2154 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2155 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2165 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2166 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2168 if (CurrentRegion->contains((*SRI).second)) { in createEntryPHI()
[all …]
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| D | GCNSchedStrategy.h | 41 const SIRegisterInfo *SRI,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 36 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
37 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
38 if (*SRI == Idx) in getSubReg()
47 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
48 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
50 return *SRI; in getSubRegIndex()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 81 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in initReg() local
82 SRI.isValid(); ++SRI) in initReg()
83 if (!MCSubRegIterator(*SRI, &RI).isValid()) in initReg()
85 Uses.insert(*SRI); in initReg()
140 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
141 SRI.isValid(); ++SRI) { in init()
142 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
146 if (R == *SRI) { in init()
155 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
160 SoftDefs.insert(*SRI); in init()
[all …]
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| /external/capstone/ |
| D | MCRegisterInfo.c | 111 uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; in MCRegisterInfo_getSubReg() local
117 if (*SRI == Idx) in MCRegisterInfo_getSubReg()
120 ++SRI; in MCRegisterInfo_getSubReg()
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| /external/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 272 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
273 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
274 ++SRI; in addLiveInsForSubRanges()
275 if (SRI == SR->end()) in addLiveInsForSubRanges()
277 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| D | CriticalAntiDepBreaker.cpp | 273 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
274 unsigned SubregReg = *SRI; in ScanInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 297 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
298 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
299 ++SRI; in addLiveInsForSubRanges()
300 if (SRI == SR->end()) in addLiveInsForSubRanges()
302 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| D | CriticalAntiDepBreaker.cpp | 290 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
291 unsigned SubregReg = *SRI; in ScanInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
138 assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); in computeConcatTransitiveClosure()
319 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
320 if (SRI == Map.end()) in computeSubRegs()
324 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
327 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1142 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1143 SRI.computeConcatTransitiveClosure(); in CodeGenRegBank()
1144 if (!SRI.ConcatenationOf.empty()) in CodeGenRegBank()
1146 SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(), in CodeGenRegBank()
[all …]
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| D | RegisterInfoEmitter.cpp | 1622 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1623 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1624 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1625 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
268 if (SRI == Map.end()) in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1449 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), in normalizeWeight() local
1450 SRE = SRM.end(); SRI != SRE; ++SRI) { in normalizeWeight()
1451 if (SRI->second == Reg) in normalizeWeight()
1454 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, in normalizeWeight()
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| D | CodeGenSchedule.cpp | 284 for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) { in collectSchedRW() local
285 assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite"); in collectSchedRW()
286 SchedReads.emplace_back(SchedReads.size(), *SRI); in collectSchedRW()
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| /external/iputils/doc/ |
| D | rdisc.sgml | 189 RFC1256</ulink>, Network Information Center, SRI International,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2798 unsigned SRI; in Select() local
2801 case 0: SRI = PPC::sub_lt; break; in Select()
2802 case 1: SRI = PPC::sub_gt; break; in Select()
2803 case 2: SRI = PPC::sub_eq; break; in Select()
2804 case 3: SRI = PPC::sub_un; break; in Select()
2807 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
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| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | iso4217raw.txt | 403 SRI LANKA Sri Lanka Rupee LKR 144
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| D | ISO4217.txt | 234 currency | LKR | Sri Lanka Rupee | LK | SRI LANKA | C
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4584 unsigned SRI; in Select() local
4587 case 0: SRI = PPC::sub_lt; break; in Select()
4588 case 1: SRI = PPC::sub_gt; break; in Select()
4589 case 2: SRI = PPC::sub_eq; break; in Select()
4590 case 3: SRI = PPC::sub_un; break; in Select()
4593 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 495 // SLI,SRI
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 497 // SLI,SRI
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| /external/cldr/tools/java/org/unicode/cldr/icu/ |
| D | idList.txt | 1416 currency; SRI
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3386 ### SRI ### subsection
|